Reduced-Precision Redundancy on FPGAs

<table>RPR filter decision signals for RPR with <svg height="15.4" id="M321" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 43.837502 15.4" width="43.837502" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> and <svg height="15.8375" id="M322" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 82.300003 15.8375" width="82.300003" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg>. The FP<sub>out</sub> signal is frozen at zero. The upper and lower comparison bound signals are calculated by adding and subtracting <svg height="15.8375" id="M323" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 18.2125 15.8375" width="18.2125" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> to and from RP<sub>out</sub>.</table>

International Journal of Reconfigurable Computing

Reduced-Precision Redundancy on FPGAs

Figure 6