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International Journal of Reconfigurable Computing
Volume 2011 (2011), Article ID 897189, 12 pages
Reduced-Precision Redundancy on FPGAs
NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA
Received 20 May 2011; Revised 29 July 2011; Accepted 29 July 2011
Academic Editor: Salvatore Pontarelli
Copyright © 2011 Brian Pratt et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- M. Cummings and S. Haruyama, “FPGA in the software radio,” IEEE Communications Magazine, vol. 37, no. 2, pp. 108–112, 1999.
- M. Caffrey, “A space-based reconfigurable radio,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '02), M. Caffrey, T. P. Plaks, and P. M. Athanas, Eds., pp. 49–53, CSREA Press, June 2002.
- Z. K. Baker, M. E. Dunham, K. Morgan et al., “Space-based FPGA radio receiver design, debug, and development of a radiation-tolerant computing system,” International Journal of Reconfigurable Computing, vol. 2010, Article ID 546217, 12 pages, 2010.
- Y. Zhang, L. Chang, G. Yang, and H. Li, “Reconfigurable-system-on-chip implementation of data processing units for space applications,” Transactions of Tianjin University, vol. 16, no. 4, pp. 270–274, 2010.
- A. K. Brown and N. Thompson, “Dynamically reconfigurable software defined radio for GNSS applications,” in Proceedings of the Software Defined Radio Forum (SDR '10), pp. 538–542, 2010.
- T. Karnik and P. Hazucha, “Characterization of soft errors caused by single event upsets in CMOS processes,” IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 2, pp. 128–143, 2004.
- P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583–602, 2003.
- C. Carmichael, “Triple module redundancy design techniques for Virtex FPGAs,” Tech. Rep. XAPP197 (v1.0), Xilinx Corporation, 2001.
- N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, “Evaluating TMR techniques in the presence of single event upsets,” in Proceedings of the 6th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD '03), p. 63, NASA Office of Logic Design, AIAA, Washington, DC, USA, Sept. 2003.
- B. Shim and N. R. Shanbhag, “Reduced precision redundancy for low-power digital filtering,” in Proceedings of the Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers,, pp. 148–152, November 2001.
- B. Shim, S. R. Sridhara, and N. R. Shanbhag, “Reliable low-power digital signal processing via reduced precision redundancy,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 497–510, 2004.
- B. Shim and N. R. Shanbhag, “Energy-efficient soft error-tolerant digital signal processing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, Article ID 1637464, pp. 336–348, 2006.
- P. Reviriego, J. A. Maestro, and S. F. Liu, “Efficient soft error-tolerant adaptive equalizers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, Article ID 5418885, pp. 2032–2040, 2010.
- J. Snodgrass, Low-power fault tolerance for spacecraft FPGA-based numerical computing, Ph.D. thesis, Naval Postgraduate School, Monterey, Calif, USA, 2006.
- M. A. Sullivan, Reduced precision redundancy applied to arithmetic operations in field programmable gate arrays for satellite control and sensor systems, M.S. thesis, Naval Postgraduate School, Monterey, Calif, USA, 2008.
- B. H. Pratt, Analysis and mitigation of SEU-induced noise in FPGAbased DSP systems, Ph.D. thesis, Brigham Young University, Provo, Utah, USA, 2011.
- M. Rice, Digital Communications: A Discrete-Time Approach, Pearson Prentice Hall, NJ, USA, 1st edition, 2009.
- E. Johnson, M. Caffrey, P. Graham, N. Rollins, and M. Wirthlin, “Accelerator validation of an FPGA SEU simulator,” IEEE Transactions on Nuclear Science, vol. 50, no. 6, pp. 2147–2157, 2003.
- B. Pratt, M. Fuller, M. Rice, and M. Wirthlin, “Reliable communications using FPGAs in high-radiation environments—Part I: characterization,” in Proceedings of the IEEE International Conference on Communications (ICC '10), pp. 1–5, Cape Town, South Africa, May 2010.