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International Journal of Reconfigurable Computing
Volume 2011 (2011), Article ID 897189, 12 pages
Reduced-Precision Redundancy on FPGAs
NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA
Received 20 May 2011; Revised 29 July 2011; Accepted 29 July 2011
Academic Editor: Salvatore Pontarelli
Copyright © 2011 Brian Pratt et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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