A Self-Checking Hardware Journal for a Fault-Tolerant  Processor Architecture

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left"></td><td align="center"> Comb. ALUTS</td><td align="center"> (Ded. Logic)</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left"> SCPC and SCHJ</td><td align="center"> 2400</td><td align="center"> (1295)</td></tr><tr><td align="left"> SCHJ alone</td><td align="center"> 1305</td><td align="center"> (726)</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

International Journal of Reconfigurable Computing

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Table 2

Table 2: A Self-Checking Hardware Journal for a Fault-Tolerant  Processor Architecture 