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Journal of Electrical and Computer Engineering
Volume 2012 (2012), Article ID 509465, 15 pages
http://dx.doi.org/10.1155/2012/509465
Review Article

Networks on Chips: Structure and Design Methodologies

1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
2Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706-1691, USA
3Department of Electrical Engineering and Graduate Institute of Electronics Enginering, National Taiwan University, Taipei 106, Taiwan

Received 18 September 2011; Accepted 1 October 2011

Academic Editor: Jiang Xu

Copyright © 2012 Wen-Chung Tsai et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.