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Journal of Electrical and Computer Engineering
Volume 2012 (2012), Article ID 691864, 24 pages
Research Article

Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections

Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095, USA

Received 17 October 2011; Revised 30 December 2011; Accepted 11 January 2012

Academic Editor: Yuan Xie

Copyright © 2012 Jason Cong et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL design frameworks. The state-of-art concurrent specification models are not suitable for modeling task-level concurrent behavior for the hardware synthesis design flow. Based on the concurrent collection (CnC) model, which provides the maximum freedom of task rescheduling, we propose task-level data model (TLDM), targeted at the task-level optimization in hardware synthesis for data processing applications. Polyhedral models are embedded in TLDM for concise expression of task instances, array accesses, and dependencies. Examples are shown to illustrate the advantages of our TLDM specification compared to other widely used concurrency specifications.