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VLSI Design
Volume 5 (1997), Issue 3, Pages 253-271
http://dx.doi.org/10.1155/1997/51094

IDDQ Testing Experiments for Various CMOS Logic Design Structures

1Duke University, Dept. of Electrical Engr., Box 90291, Durham, NC 27708-0291, USA
2ISS CAD Inc., USA
3University of North Carolina, Charlotte, USA
4lBM, Charlotte, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In this paper, we present two studies. The first study constitutes an assessment of the effectiveness of IDDQ (quiescent power supply current) in detecting transistor-level defects for three CMOS logic design styles. This study was carded out by designing, simulating, fabricating, and testing CMOS devices with built-in defects. The second study involves an assessment of IDDQ in a production-type environment and the effect of bum-in on IDDQ levels. This study was carried out in a production facility. The results show that IDDQ testing can detect some types of defects in precharge and pseudo-NMOS circuits but may require partitioning circuitry for the latter.