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VLSI Design
Volume 5 (1997), Issue 3, Pages 273-284
http://dx.doi.org/10.1155/1997/97381

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

1lnstituto Nacional de Astrofísica, Optica y Electrónica, Grupo de Diseño de CI, Apdo. Postal 51 y 216, Puebla 72000, Pue., Mexico
2Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrónica, Diagonal 649, Planta 9, Barcelona 08028, Spain

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is characterized in order to investigate its detectability by IDDQ . The defect is modeled at the circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent power supply current consumption (IDDQ ) of the defective circuit. The testing implications on the type of defective gate are studied. Experimental measures have been made on basic CMOS combinational modules designed with intentional floating gate defects. A good agreement is observed between the simulation results and the experimental data. A conventional ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate defects by IDDQ Testing.