VLSI Design
Volume 7 (1998), Issue 1, Pages 97-110
doi:10.1155/1998/38483

Placement and Routing for Performance-Oriented FPGA Layout

Michael J. Alexander,1 James P. Cohoon,2 Joseph L. Ganley,3 and Gabriel Robins2

1School of Electrical Engineering and Computer Science, Washington State University, Pullman 99164-2752, WA, USA
2Department of Computer Science, University of Virginia, Charlottesville 22903-2442, VA, USA
3Cadence Design Systems, lnc., San Jose 95134-1937, CA, USA

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, and Gabriel Robins, “Placement and Routing for Performance-Oriented FPGA Layout,” VLSI Design, vol. 7, no. 1, pp. 97-110, 1998. doi:10.1155/1998/38483