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VLSI Design
Volume 5 (1998), Issue 4, Pages 313-331
http://dx.doi.org/10.1155/1998/63013

Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework

Department of Electrical, Computer and Systems Engineering, Boston University, Boston, MA 02215, USA

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In this paper we present an approach for combining on-line concurrent checking (CC) with off-line built-in self-test (BIST). We will show that a reduction of an aliasing probability can be obtained for manufacturing testing by monitoring the output of a concurrent checker and a reduction of a probability of not detecting an error in the computing mode can be obtained by a short periodic BIST. We will present a technique for optimal selection of error-detecting codes for combined on-line CC and off-line space-time compression of test responses for BIST and estimate probabilities of not detecting an error for the approach based on integrating CC and BIST. We also present a technique for on-line error-detection in space-time compressors of test responses for BIST.