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VLSI Design
Volume 5 (1998), Issue 4, Pages 347-356
http://dx.doi.org/10.1155/1998/67574

Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability

SATCON GmbH, Satellitenkommunikationsgesellschaft, Potsdamer Str. 7-9, Teltow 14513, Germany

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In self-checking systems, checkers usually do not receive all code words during normal operation. Missing code words may prevent a checker from achieving the totally self-checking property. The paper presents a novel approach to the design of embedded parity and two-rail checkers that allows a checker to receive all code words irrespective of the set of code words that is provided by the functional circuit. A checker gets all code words by an LFSR while at the same time it monitors the output of the functional circuit. Additionally, the LFSR is able to capture the error patterns of noncode words. Captured error patterns will be modified since they will cycle through the LFSR. Thus, noncode words that are not detected due to undetected checker faults can be detected in later instances of time. The proposed method can be extended to the design of checkers for linear codes.