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VLSI Design
Volume 9 (1999), Issue 1, Pages 29-54
http://dx.doi.org/10.1155/1999/29035

Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing

Department of Electrical and Computer Engineering, New Jersey Institute of Technology, University Heights, Newark 07102, New Jersey, USA

Received 5 May 1997

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Extensive comparative analysis is carried out of various mesh-connected architectures that contain sparse broadcast buses for low-cost, high-performance parallel computing. The two basic architectures differ in the implementation of bus intersections. The first architecture simply allows row/column bus crossovers, whereas the second architecture implements such intersections with switches that introduce further flexibility. Both architectures have lower cost than the mesh with multiple broadcast, which has buses spanning each row and each column, but the former architectures maintain to high extent the powerful properties of the latter mesh. The architecture that employs switches for the creation of separable buses is even shown to often perform better than the higher-cost mesh with multiple broadcast. Architectures with separable buses that employ store-and-forward routing often perform better than architectures with contiguous buses that employ the high-cost wormhole routing technique. These architectures are evaluated in reference to cost, and efficiency in implementing several important operations and application algorithms. The results prove that these architectures are very promising alternatives to the mesh with multiple broadcast while their implementation is cost-effective and feasible.