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VLSI Design
Volume 9 (1999), Issue 1, Pages 17-28
http://dx.doi.org/10.1155/1999/71739

Single Step Undirected Reconfigurable Networks

1Dept. of Comp. Sci., Haifa U, Haifa, Israel
2Department of Computer Science, Technion, Haifa 32000, Israel

Received 5 May 1997

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The reconfigurable mesh (RN-MESH) can solve a large class of problems in constant time, including problems that require logarithmic time by other, even shared memory, models such as the PRAM with a similar number of processors [3]. In this work we show that for the RN-MESH these constants can always be reduced to one, still using a polynomial number of processors. Given a reconfigurable mesh that computes a set of values in constant time, we show that it can be simulated by a single step reconfigurable mesh with maximum size that is polynomial in the size of the original mesh. The proof is constructive, where the construction of the single step RN-MESH holds for the relatively weak undirected RN-MESH model. In this model broadcasts made on buses arrive at all nodes that belong to the undirected connected component of the transmitting processor. A result similar to the one that is obtained in this work was previously obtained for the directed reconfigurable mesh model (DRN) [5]. However, the construction for the DRN-MESH relies on the fact that the buses are directed, and thus cannot be applied to the undirected case. In addition, the construction presented here is simpler and uses significantly fewer processors than the one obtained for the DRN-MESH.