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VLSI Design
Volume 12 (2001), Issue 2, Pages 205-219
http://dx.doi.org/10.1155/2001/31269

A Fast and Accurate Method of Power Estimation for Logic Level Networks

1VLSI Design Lab, Dept. of Electrical and Computer Eng., University of Patras, Patras 26110, Greece
2VLSI Design and Testing Center, Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi 67100, Greece

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A method for estimating the power consumption of multilevel combinational networks is introduced. The proposed method has as inputs the signal probabilities, the data correlations of the primary inputs and the structure of the circuit, and consists of two major steps: (i) the calculation of the switching activity on an individual gate and (ii) the calculation of the switching activity of any node of the network. The foregoing step includes the derivation of novel formulas for calculating the switching activity of basic gates. The latter step includes the development of an algorithm, which propagates the signal probabilities through the network and calculates the switching activity of any logic node. The proposed method provides accurate switching activity values performing their calculation in reduced time interval. The experimental results prove that the proposed method achieves significant reduction up to 50% in terms of multiplications compared to method of [6].