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VLSI Design
Volume 12 (2001), Issue 2, Pages 205-219
http://dx.doi.org/10.1155/2001/31269

A Fast and Accurate Method of Power Estimation for Logic Level Networks

1VLSI Design Lab, Dept. of Electrical and Computer Eng., University of Patras, Patras 26110, Greece
2VLSI Design and Testing Center, Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi 67100, Greece

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

G. Theodoridis, S. Theoharis, D. Soudris, and C. Goutis, “A Fast and Accurate Method of Power Estimation for Logic Level Networks,” VLSI Design, vol. 12, no. 2, pp. 205-219, 2001. doi:10.1155/2001/31269