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VLSI Design
Volume 13 (2001), Issue 1-4, Pages 169-173
http://dx.doi.org/10.1155/2001/63643

Non-Equilibrium Hole Transport in Deep Sub-Micron Well-Tempered Si p-MOSFETs

Device Modelling Group, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, UK

Copyright © 2001 Hindawi Publishing Corporation.

Abstract

As MOSFETs are scaled to deep submicron dimensions non-equilibrium, near ballistic, transport in p-MOSFETs becomes important. Recent experimental data indicates that as MOSFETs are scaled the performance gap between n and p-channel shrinks. Nonequilibrium transport effects and performance potentials of ‘Well Tempered’ Si p- MOSFETs with gate lengths of 50 and 25 nm are studied. Monte Carlo and calibrated Drift Diffusion simulations of these devices provide a quantitative estimate of the importance and the influence of non-equilibrium transport on submicron device performance. A possible explanation for the closing performance gap between n- and p-channel MOSFETs is offered.