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VLSI Design
Volume 13 (2001), Issue 1-4, Pages 111-115
http://dx.doi.org/10.1155/2001/90787

Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability

1Beckman Institute, Department of Electrical and Comuter Engineering and Department of Physics, University of Illinois, Urbana 61801, IL, USA
2Department of Electrical Engineering, University of Texas, Austin 78712-1100, TX, USA

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.