About this Journal Submit a Manuscript Table of Contents
VLSI Design
Volume 2007 (2007), Article ID 50285, 12 pages
http://dx.doi.org/10.1155/2007/50285
Research Article

Area and Power Modeling for Networks-on-Chip with Layout Awareness

1Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy
2Department of Electronics and Information Scince (DEIS), University of Bologna, Bologna 40136, Italy
3Department of Mathematics and Information Science, University of Cagliari, Cagliari 09123, Italy

Received 1 November 2006; Revised 2 February 2007; Accepted 1 March 2007

Academic Editors: Maurizio Palesi and Maurizio Palesi

Copyright © 2007 Paolo Meloni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Networks-on-Chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.