VLSI Design

A Video Specific Instruction Set Architecture for ASIP design

Low-Power Built-In Self-Test Techniques for Embedded SRAMs

Eight-Bit Semiflash A/D Converter

On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

Robustness of Transmultiplexed Images

Power Consumption and BER of Flip-Flop Inserted Global Interconnect

A -Enhanced 3.6 GHz, Tunable, Sixth-Order Bandpass Filter Using 0.18 m CMOS

Networks-on-Chip: Emerging Research Topics and Novel Ideas

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Area and Power Modeling for Networks-on-Chip with Layout Awareness

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

VLSI Design

Table of Contents

Table of Contents: 2007

A Video Specific Instruction Set Architecture for ASIP design

Low-Power Built-In Self-Test Techniques for Embedded SRAMs

Eight-Bit Semiflash A/D Converter

On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

Robustness of Transmultiplexed Images

Power Consumption and BER of Flip-Flop Inserted Global Interconnect

A -Enhanced 3.6 GHz, Tunable, Sixth-Order Bandpass Filter Using 0.18 m CMOS

Networks-on-Chip: Emerging Research Topics and Novel Ideas

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Area and Power Modeling for Networks-on-Chip with Layout Awareness

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip