Abstract
An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both
the coarse and the
fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most
significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are
evaluated by the same array of comparators. The auto-zeroed comparators also perform the
function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no
sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result,
a moderate conversion speed has been combined with a drastically reduced power
consumption. The ADC was fabricated in a standard 0.6