Abstract
A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect
scheme is proposed. This scheme is scalable and suitable for transferring data across
different clock domains such as those in “many-core” SoCs and in
3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronization
scheme. Removing the intermediate flip-flops in the SSMC scheme enables better averaging
of delay variations across the whole interconnect, which reduces bit-rate degradation due to
within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates