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VLSI Design
Volume 2007 (2007), Article ID 95859, 10 pages
http://dx.doi.org/10.1155/2007/95859
Research Article

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

1Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven 5600 MB, The Netherlands
2Computer Engineering, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Delft 2600 GA, The Netherlands
3SOC Architectures and Infrastructure, Research, NXP Semiconductors, Eindhoven 5656 AE, The Netherlands

Received 16 November 2006; Accepted 6 February 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Andreas Hansson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions introduce message dependencies that affect deadlock properties of the SoC as a whole. Even when NoC and IP dependency graphs are cycle-free in isolation, put together they may still create cycles. Traditionally, SoCs rely solely on request-response protocols. However, emerging SoCs adopt higher-level protocols for cache coherency, slave locking, and peer-to-peer streaming, thereby increasing the complexity in the interaction between the NoC and the IPs. In this paper, we analyze message-dependent deadlock, arising due to protocol interactions between the NoC and the IP modules. We compare the possible solutions and show that deadlock avoidance, in the presence of higher-level protocols, poses a serious challenge for many current NoC architectures. We evaluate the solutions qualitatively, and for a number of designs we quantify the area cost for the two most economical solutions, strict ordering and end-to-end flow control. We show that the latter, which avoids deadlock for all protocols, adds an area and power cost of 4% and 6%, respectively, of a typical Æthereal NoC instance.