FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

Table 4

Resource utilization of the Simple Observer (SO) and Composite Observer (CO) using Quartus II tool.

	SO	CO
Family	Cyclone II	Cyclone II
Device	EP2C8T144C8	EP2C8T144C8
Total logic elements	265/8,256 (3%)	2,431/8,256 (29%)
Combinational with no register
Combinational with a register	206	2167
Logic element usage by number of LUT inputs	59	264
4 input functions	0	6
3 input functions	240	2053
<=2 input functions	25	372
Combinational cells for routing	0	19
Logic elements by mode
Normal mode	14	299
Arithmetic mode	251	2132
Total registers	59/8,256 (<1%)	264/8,256 (3%)
Total LABs	24/516 (4%)	207/516 (40%)
Embedded Multiplier 9-bit elements	16/36 (44%)	36/36 (100%)