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VLSI Design
Volume 2010 (2010), Article ID 512312, 14 pages
http://dx.doi.org/10.1155/2010/512312
Research Article

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

1Department of Electrical Engineering, Indian Institute of Information Technology Design & Manufacturing Kancheepuram, IIT Madras campus, Chennai-600036, India
2Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai-600036, India

Received 10 June 2009; Accepted 20 October 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 K. Selvajyothi and P. A. Janakiraman. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a single chip FPGA (Altera Cyclone II) controlled single phase inverter, programmed for the reduction of harmonics in the output voltage. Separate composite digital observers have been designed for extracting the fundamental and harmonic components of the voltage and the highly distorted current signals, particularly when the inverter supplies nonlinear loads. These observers have been embedded into the FPGA along with the controllers and I/O interfaces. The multiple observers yield very pure in-phase and quadrature voltage signals for use in the outer loop and similar signals for stabilizing the inner current loop. The Inverter could be modeled as a feed back control system with the fundamental component of the voltage as the desired output while the voltage harmonics take the role of noise creeping into the output. To obtain a very low total harmonic distortion in the voltage waveform, the well-known control strategy of using a very large feed back around the noise signal has been employed.

1. Introduction

Stand-alone inverters are commonly used in the case of power failure, to deliver power for critical loads, which demand purely sinusoidal voltage at the specified magnitude, frequency, and low total harmonic distortion (THDv). The THDv in industry should not exceed 5% as per the guidelines given in the IEEE Standard 519-1992. Fixed passive filters may not perform well, particularly when the operating frequency drifts far away from the set resonance frequency. Alternatively, active filters can be employed. Many control methods have been proposed basically for obtaining pure sinusoidal output with good voltage regulation and fast dynamic response [19]. Sinusoidal pulse width modulation (SPWM) schemes for stand-alone inverters have been shown to perform well with linear loads [10]. However, with nonlinear loads the SPWM scheme does not guarantee low distortion in the output voltage. The availability of low cost microprocessors has led to discrete-time methods, such as repetitive control [1, 2], sliding mode control [3], and deadbeat control [4, 5] to improve the performance. To get zero steady-state error in the output voltage and fast response virtual inductor, capacitor and a resistor were used in [6], while internal model control scheme (IMC) was employed in [7]. The control methods presented in [8, 9] employ two-feedback control loops. The inner loop is used for current control and the outer loop is used for voltage control. Many of these methods have not specifically considered the reduction in distortion due to nonlinear loads.

The emergence of FPGAs has drawn much attention due to their shorter design cycle, lower cost, and higher density. The simplicity and programmability of FPGAs make them a most favorable choice for prototyping digital systems. When comparing the dynamic performance and control capabilities in PWM-controlled Power converters FPGA-based digital techniques are better than DSPs [11].

Basically a Luenberger observer (simple observer) can be used for obtaining the filtered fundamental component from the periodic output voltage and current waveforms, which leads to the indirect estimation of the total harmonics in the output voltage due to the nonlinear loads [12]. The Inverter can be modeled as a feed back control system with the fundamental component as the desired output, while the harmonics take the role of noise creeping into the output. The well-known control strategy of using a large feed back around the noise signal was employed, to reduce the effect of noise at the output. The net effect is a smoother output voltage showing negligible total harmonic distortion, even with nonlinear loads. In this paper, an attempt has been made to show the usefulness of controlling inverters by composite observers [13, 14] rather than by using simple observers. The typical composite observer provides the pure filtered fundamental in-phase signal along with the companion quadrature signal. Alongside, the various harmonics are also estimated as instantaneous in-phase and quadrature signal pairs [13, 14]. The composite observer has a repetitive parallel structure, which can be easily implemented in an FPGA.

2. System Overview

An inverter supplying a rectifier with an RC load is shown in Figure 1. The parameters of the inverter are listed in Table 1.

tab1
Table 1: Inverter system parameters for simulation.
512312.fig.001
Figure 1: Single phase inverter circuit under rectifier load with RC filter.

The proposed control scheme can be split into two parts:

(a) use of in-phase and quadrature fundamental output voltage and current signals for conventional D-Q control, (b) reduction of the distortion in the output voltage waveform, by feedback of voltage harmonic signals.
2.1. Design of Discrete Composite Observer

Observability means the ability to estimate the initial state from an infinite number of input-output observations. Any periodic signal 𝑦(𝑘𝑇) rich in harmonics and a DC bias can be modeled as if 𝑦(𝑘𝑇) emanates from a system described by

𝑥((𝑘+1)𝑇)=𝐴𝑥(𝑘𝑇),𝑦(𝑘𝑇)=𝐶𝑡𝑥(𝑘𝑇),(1) where 𝐴𝐴=000000𝐴100000𝐴200000𝐴𝑚00000𝐴𝑁;𝐴0[𝐶]=1,𝑡=.1101010(2) The typical 𝑚th subblock is given by

𝛼𝐴𝑚=𝑚𝛼𝑚1𝛼𝑚+1𝛼𝑚,where𝛼𝑚=cos𝑚𝜔1𝑇(3) with state vector 𝑥𝑚(𝑘𝑇) and output variable 𝑦𝑚(𝑘𝑇) defined by

𝑥𝑚𝑥(𝑘𝑇)=𝑚1𝑥(𝑘𝑇)𝑚2(𝑘𝑇),𝑦𝑚(𝑘𝑇)=𝐶𝑡𝑚𝑥𝑚𝐶(𝑘𝑇),𝑡𝑚=10for𝑚=1,2,3,,𝑁,𝐶0=1.(4)

The Discrete Composite Observer is a closed loop model of the system, with an open loop part consisting of 𝑁 controlled digital oscillators as sub-blocks, one for each harmonic, arranged in the parallel format along with a DC block. The 𝑚th block of the observer can be modeled with a state vector ̂𝑥𝑚(𝑘𝑇) and an output variable ̂𝑦𝑚(𝑘𝑇) defined by:

̂𝑥𝑚(𝑘𝑇)=̂𝑥𝑚1(𝑘𝑇)̂𝑥𝑚2(𝑘𝑇),̂𝑦𝑚(𝑘𝑇)=̂𝑥𝑚1(𝑘𝑇),̂𝑥𝑚((𝑘+1)𝑇)=𝐴𝑚̂𝑥𝑚(𝑘𝑇)+𝐷𝑚𝑒(𝑘𝑇),̂𝑦𝑚(𝑘𝑇)=𝐶𝑡𝑚̂𝑥𝑚𝐷(𝑘𝑇);𝑚=0,1,2,𝑁;𝑚=𝑑𝑚1𝑑𝑚2for𝑚=1,2,3,,𝑁,𝐷0=𝑑0.(5) The observation error 𝑒(𝑘𝑇) is defined by

𝑒(𝑘𝑇)=𝑦(𝑘𝑇)̂y(𝑘𝑇)=𝐶𝑡[]𝑥(𝑘𝑇)̂𝑥(𝑘𝑇)=𝐶𝑡𝐸(𝑘𝑇),(6) where

̂𝑦(𝑘𝑇)=𝑚=𝑁𝑚=0̂𝑦𝑚[](𝑘𝑇),𝐸(𝑘𝑇)=𝑥(𝑘𝑇)̂𝑥(𝑘𝑇).(7) The sum of all the individual (𝑁+1) output variables ̂𝑦𝑚(𝑘𝑇) shown in (7) is the scalar output of the observer.

Under steady state, ̂𝑦(𝑘𝑇)𝑦(𝑘𝑇) as 𝑘.

Each sub-block has two fixed parameters 𝐷𝑚=(𝑑𝑚1,𝑑𝑚2) and only one tunable parameter 𝛼𝑚. This facilitates easy tuning of the observer under wandering frequency conditions. Only one multiplier is required rather than two required for tuning the two-dimensional sub blocks [14].

512312.fig.002
Figure 2: Structure of Discrete Composite Voltage Observer.

The composite observer defined so far can be concisely written as

[𝐴][𝐷]̂𝑥((𝑘+1)𝑇)=̂𝑥(𝑘𝑇)+𝑒(𝑘𝑇),̂𝑦(𝑘𝑇)=𝐶𝑡̂𝑥(𝑘𝑇),(8) where 𝐷 the gain vector is given by

𝑑𝐷=0,𝑑11,𝑑12𝑑21,𝑑22𝑑𝑚1,𝑑𝑚2𝑑𝑁1,𝑑𝑁2𝑡.(9) The 2𝑁+1 observation-error-vector [𝐸(𝑘𝑇)=𝑥(𝑘𝑇)̂𝑥(𝑘𝑇)] is composed of the individual estimation errors in the DC, fundamental as well as the real and imaginary (orthogonal) harmonic components of the given signal.

Using (1), (6), and (8), we get

𝐸((𝑘+1)𝑇)=𝐴DC𝑡𝐸(𝑘𝑇).(10) The characteristic equation, for the error-difference equation in (10), can be obtained in the 𝑧-domain as

Det𝑧𝐼𝐴+DC𝑡=0,(11) where 𝐼 is a (2𝑁+1)×(2𝑁+1) Identity matrix.

The (2𝑁+1) roots of the characteristic equation, which are also defined as the observer poles, can be located within the unit circle in the 𝑧-plane (Figure 3). Such an “observer pole placement” makes the closed loop observer stable and the norm of the error vector 𝐸 vanishes as the time tends to infinity, that is, 𝐸(𝑘𝑇)0, as 𝑘.

512312.fig.003
Figure 3: Poles of Discrete Observer for (2𝑁+1)=15.

Let the 2𝑁+1 closed loop poles to be equidominant and located such that z = 𝑒𝛿𝑇 for m = 0 and

𝑧=𝑒𝛿𝑇𝛼𝑚±𝑗𝛽𝑚,(12) where 𝛼𝑚=cos(𝑚𝜔1𝑇),𝛽𝑚=sin(𝑚𝜔1𝑇) for 𝑚=1,2,,𝑁, 𝛼0=1,𝛽0=0,𝛿=𝑎𝜔1,𝑎>0, which controls the observation speed, and 𝜔1 is the Fundamental frequency.

In the structure chosen, for a typical sub-block “𝑚”, the state variable ̂𝑥𝑚1(𝑘𝑇) will ultimately merge with the 𝑚th harmonic in the input signal. Each sub-block in the observer acts like a comb filter, accepting the signal of the respective tuned frequency and rejecting all other harmonic frequencies. The state variable ̂𝑥𝑚2(𝑘𝑇) will exhibit a phase-shift of 90° with respect to the signal ̂𝑥𝑚1(𝑘𝑇). Further, a magnitude scaling factor 𝑔𝑚=(𝛼𝑚1)/𝛽𝑚 needs to be introduced for this orthogonal signal, for equalizing the amplitudes of the two signals ̂𝑥𝑚1(𝑘𝑇) and ̂𝑥𝑚2(𝑘𝑇). The observer can be tuned when the frequency of the input signal 𝑦(𝑘𝑇) to the observer drifts. This is done by adjusting the parameter 𝛼𝑚 using the correlation between the error signal 𝑒(𝑘𝑇) and the fundamental quadrature signal ̂𝑥12(𝑘𝑇) [14]. The fundamental block in the composite observer for 𝑎=1 is shown in Figure 4. This “𝑠” domain specification corresponds to |𝑧| = 0.9758 in the digital domain (see Figure 3), for a sampling frequency of 12.8 kHz. The various harmonic blocks also have the same structure. However, the quadrature signal (“cos”) need not be taken out for the harmonics, thereby reducing the number of gain elements required in the FPGA realization. The structure of the DC block is shown in Figure 5. The gains in these blocks correspond to real part of observer poles at 𝑎=1. The composite observer used for voltage signal processing is shown in Figure 6.

512312.fig.004
Figure 4: Structure of the Fundamental block in the Discrete Composite Voltage Observer.
512312.fig.005
Figure 5: DC block in the Discrete Composite Voltage Observer.
512312.fig.006
Figure 6: Structure of Discrete Composite Voltage Observer.

The current observer can also be made to have the same structure as the voltage observer. However, to reduce the number of DSP elements required, only the DC block and the fundamental block were used for the current observer as shown in Figure 7.

512312.fig.007
Figure 7: Structure of Current Observer.
2.2. D-Q Control Using Fundamental Components

In a 2-phase system the steady-state errors could be overcome by introducing DC reference-commands and the corresponding DC variables for representing the sinusoidal trajectories. When DC variables converge to constant values under steady-state, it is easier to make the steady-state error zero by including a conventional PI controller in the control loop.

Using a discrete composite voltage observer, having DC and odd harmonic blocks up to 11th (0,1,3,,11), the in-phase (sine) and the fictitious quadrature (cosine) fundamental voltage signals of the inverter can be derived. Applying the Park transformation, in a manner which is analogous to 2-phase systems, these components can be transformed to “D-Q” coordinates. The Park transform requires unit sine and cosine reference signals which are generated internally for the stand-alone inverters:

𝑉𝑑𝑉𝑞=𝜔sin1𝑡𝜔cos1𝑡𝜔cos1𝑡𝜔sin1𝑡𝜔sin1𝑡+𝜑2𝜔cos1𝑡+𝜑2.(13) Ideally, the load voltage is expected to contain only the fundamental components, whereas all the other harmonic components including random noise in the voltage loop must be zero. Now, the estimation speed of the observer depends on the pole-location. In the continuous domain, observer poles closer to the origin of the 𝑠-plane make the estimation sluggish, while the poles located farther from the origin of the 𝑠-plane make the observer faster. On the other hand, for a digital version of the observer, placing the poles closer to the origin in the “𝑧” plane can speed up the estimation while placing the poles near to the unit circle makes it sluggish. In any case, very high-speed observers show a heavy distortion in the extracted fundamental and other components. Placing the observer poles closer to the unit circle in the 𝑧-domain (closer to origin of the 𝑠-plane) makes the extracted fundamental component pure and accurate, at the cost of increased time for estimation, which may even lead to instability of the voltage control system. The steady-state error-vector between the desired 𝑑-𝑞 components and the actual 𝑑-𝑞 components obtained from the composite voltage-observer is processed through PI controllers to obtain 𝑑-𝑞 current references. In the simulation and experimental studies presented in this paper, the decay factor “𝑎” for voltage observer and current observer were set at 1.

The control scheme for reducing harmonics in the inverter is shown in Figure 8. The steady-state error-vector [𝑒vd,𝑒vq] between the desired D-Q component values and the actual D-Q component values obtained from the voltage-observer is processed through PI controllers to obtain D-Q current references. Similarly, using another simple observer, the fundamental in-phase and fictitious quadrature current signals are estimated. This facilitates transformation of the current to the D-Q frame. The current error-vector [𝑒Id,𝑒Iq] in the D-Q frame is processed by simple gain elements (k) even though PI or lead type compensators could have been used. The steady outputs of the two controllers in the current loop are converted into the in-phase and quadrature time signals, via the single-phase-inverse Park transform. The two time signals are added to get the sinusoidal reference signal for pulse width modulation as shown in Figure 8. Without any compensation for harmonics, the output voltage is heavily distorted for a “nonlinear load”, consisting of a rectifier driving a RC load (10Ω1mF). The THDv is about 15.34% even though the control signal appears to be a pure sine wave. The distorted output voltage, pulsed load current, and the control voltage are shown in Figure 9. The distortion is mainly due to the voltage drop caused by the harmonic currents in the series R-L filter of the inverter.

512312.fig.008
Figure 8: Schematic of the Proposed Control Strategy for the inverter.
512312.fig.009
Figure 9: Distorted output voltage, current, and control signal with no harmonic feedback.
2.3. Series Compensation by Harmonic Feedback

Let us consider the harmonics creeping into the output due to the voltage drop in the inductor as shown in Figure 10(a). The sum of all the harmonics can be assumed to be equivalent to a noise signal, superimposed on the fundamental component. In Figure 10(b), both the noise and the signal have unity gain. If a control loop could be built around the noise signal, with a high feedback gain “” for the noise alone, as shown in Figure 10(c), its effect in the output can be made negligible. This requires a highpass filter, which can be realized from the composite voltage observer, designed for extracting the various harmonics.

fig10
Figure 10: (a) Voltage drop across the inductor. (b) Equivalence of harmonic distortion to noise. (c) Attenuation of noise in closed loop.
512312.fig.0011
Figure 11: Control signal which yields a pure sine Output.

The high-frequency harmonic signal, which is devoid of the fundamental component and DC, can be fed back with a high gain “” for reducing the distortion as shown in Figure 8. While the fundamental gain remains unaffected at unity, the closed loop gain (𝐾nf) for the harmonics becomes smaller:

𝐾nf=1(1+).(14)

For example, when =20, the effect of noise with this local loop reduces to 𝐾nf/1.0 = 5%.

Interestingly, due to harmonic feedback, the control signal becomes enriched with harmonics, as shown in Figure 11. In contrast, the output voltage waveform becomes a purer sine wave as shown in Figure 12.

512312.fig.0012
Figure 12: Load voltage signal after harmonic feed-back while supplying a current to a nonlinear load.
2.4. Model of the Proposed Control System

A model for the fundamental components, as shown in Figure 13, of the inverter control system is obtained on the basis of the following assumptions. Since the loads may be nonlinear, the steady-state fundamental components of the voltage and current signals alone are taken into account for modeling. The inverter is assumed to drive near-unity power factor loads, which makes the system somewhat decoupled as far as the direct and the quadrature channels are concerned. So, we need to consider either the direct axis channel or the quadrature axis channel for analysis. The pulse width modulating (PWM) block is modeled as a unity-gain (𝑘1) saturation-block, which feeds into a linear gain, of value = 24, the battery voltage. The input saturation level of PWM block is the peak of the carrier signal. The LC filter with resistive load can also be included in the model. The observer is equivalent to a lowpass filter in the 𝑑 or 𝑞 domains. A simple proportional controller with a fixed gain setting (say 1.5) is sufficient for the current loop because the PI controller in the voltage-loop will guarantee the accuracy of the amplitude of the output voltage, in the linear operating region. The real part of the current-observer pole was placed at 0.1ω. This is slow enough to filter out the harmonics of the current under nonlinear loads like a rectifier with RC filter. The real part of the voltage-observer pole is 10 times faster than the current-observer pole and is placed at 1ω. The slower current loop causes reduced phase margin and increased overshoot under transient conditions. The stability of the total control system depends mainly on the feedback factor “”, observer pole location, and the PI controller settings of the voltage loop. While some of the parameters listed above can be intuitively assigned, the major problem remaining is the design of the PI controller so that the control system would remain stable.

512312.fig.0013
Figure 13: Block diagram for any one channel (𝑉𝑑 or 𝑉𝑞).
512312.fig.0014
Figure 14: Root Locus for determining integral constant of the PI controller.
512312.fig.0015
Figure 15: Validation of Model for a step disturbance in 𝑉dref.

Sketching the root locus and enlarging it around the origin (Figure 14) reveal one real pole and a complex closed loop pole pair being dominant. By adjusting the zero of the PI controller, all these three poles can be made to have the same negative real part or remain equally dominant as the closed loop gain tends to infinity. For Req = 5.7 Ω, =20, the settings are Kp = 0.56 and Ki = 81. It is appropriate to carry out the stability analysis in the 𝑧-domain.

2.5. Validation of Model

For a step change in the reference 𝑉𝑑, the response of the model and system is shown in Figure 15. The system and the model initial conditions were different. However after convergence, the incremental responses of the system and the model coincide reasonably well.

3. FPGA Implementation Schematic of the Controller

The overall hardware implementation circuit of the single phase inverter is shown in Figure 16. The measured output voltage and current are normalized to unity using 𝑔𝑣 and 𝑔𝑖, which include voltage divider as well as the analog amplifier gains. Inside the FPGA the maximum voltage and current variables are made equal to unity. Hence the same setup could be easily extended to any voltage or current levels, by suitably adjusting the external range setting devices.

512312.fig.0016
Figure 16: Overall Hardware implementation circuit of the inverter.

The implementation consists of two separate ADCs for feeding in the load voltage and current into the control circuit as shown in Figure 17. A serial +5V, 12-bit, MSOP-8 package analog-to-digital converter ADS7835 was interfaced with Cyclone II FPGA. Handshaking between FPGA and ADS7835 is through 3 signals named Convert, Clock, and Data. The Convert and Clock are input signals to ADC from FPGA, while the converted Data goes into the FPGA. Since the level of the digital I/O signals for the FPGA is at 3.3 V and the ADC operates at 5 V, a digital buffer (16 pin 74HC366) has been provided for the two channels. The serial data from ADS7835 has been converted into 12-bit parallel data in the integer format in the FPGA, which is shown in Figure 17. Since the integer signals are to be normalized to 18-bits floating point, that is, [315], further conversion to floating point is necessary which is illustrated in Figure 18. Bit-by-bit extraction and addition in the floating point has been carried out for achieving this. These two procedures were incorporated as subsystems.

512312.fig.0017
Figure 17: ADC Program for ADS 7835 in DSP Builder.
512312.fig.0018
Figure 18: Integer to floating point block.
512312.fig.0019
Figure 19: Generation of D-Q Voltage and Current Signals using the Output of the Inverter.

The measured current and the voltage variables available in the floating point format are fed to separate observers, one for voltage and the other for the current as shown in Figure 19. The basic unit sinusoidal signal is generated by using a look up table and an address-generating counter, triggered by the same pulses, which drive the observers. The arrangement is shown in Figure 20. A 50 Hz unit sine wave is generated, by creating 256 data entries, obtained by sampling off-line, 256 times a full unit sine wave. The LUT which holds the data in the [315] floating format has an 8-bit address space, which can be accessed by an 8-bit address counter. The 12.8 kHz enabling pulses for the address counter are derived from a mod 313 counter, whose clock ticks at 4 MHz. The unit sine wave from the LUT is fed to an observer of the structure shown in Figure 4, so as to get the unit sine and cosine reference signals as shown in Figure 20. The extracted in-phase and quadrature fundamental signals from the voltage or current observer and the lookup table generated unit sine and cosine waves are used to derive the D-Q components of load voltage or current through the Park transform. A typical Park Transform block is shown in Figure 21. The references 𝑉dref and 𝑉qref are set as required in floating point format. The 𝑉𝑑 and 𝑉𝑞 feedback signals are derived from the voltage observer, after Park transformation as explained earlier. The errors in 𝑉𝑑 and 𝑉𝑞 are processed through separate PI controllers. The outputs of these PI controllers are taken to be the 𝐼dref and 𝐼qref signals for inner current loop. The current error signals are processed by proportional controllers and further converted into sinusoidal control signal via single-phase-inverse park transform as shown in Figure 22.

512312.fig.0020
Figure 20: Internal Generation of Unit sine and cosine signals.
512312.fig.0021
Figure 21: Computation of D-Q components (Park Transform).
512312.fig.0022
Figure 22: Fundamental Control signal generation via single-phase-inverse Park transform.
512312.fig.0023
Figure 23: PWM pulse generation from the Control Signal.

Along with this control signal, voltage harmonics are fed back with a large gain and then filtered to remove very high-frequency noise corrupting the control signal. A 10 kHz triangular carrier (dither) signal is used for the generation of sinusoidal PWM pulses required by the power MOSFETs of the inverter. The schematic is shown in Figure 23.

4. Experimental Results

Using the Altera DSP Builder, a digital version of the control scheme was designed and implemented in a Cyclone II (Altera) FPGA. The load voltage and current corresponding to a nonlinear load, with a harmonic feedback gain in the range 0<<20, were recorded, for validating the simulations. Figure 24(a) shows the heavily distorted load voltage (THDv 16.4%) for a nonlinear current since no harmonic feedback compensation was provided. Similarly even when a composite voltage observer is used along with a simple current observer, as long as no harmonic feedback compensation is provided, the voltage waveform will be distorted (THDv 15.29%) for a nonlinear load (Figure 24(b)). In Figure 25(a), the harmonic feedback gain “” was set at 20, while supplying a rectifier load of 10Ω1mF. It is seen that even a simple voltage observer gives a pure sine wave output, showing a THD of 1.2% When a composite voltage observer is used along with a simple current observer, the voltage waveform is still purer showing a THD of 0.98% (Figure 25(b)). Even though this result is attractive, very large harmonic feedback gains make the control system sluggish and reduce the stability margin appreciably. From Table 2, it is clear that a harmonic feedback gain of 5 is sufficient to get a THD of 4.67%.

tab2
Table 2: % THDv of the inverter output voltage with the two different schemes.
fig24
Figure 24: (a) Distorted output voltage waveform when a simple Voltage Observer and a simple Current Observer are used. (b) Distorted output voltage waveform when a Composite Voltage Observer and a simple Current Observer are used.
fig25
Figure 25: (a) Pure output voltage waveform when a Simple Voltage Observer and a simple Current Observer are used. (b) Pure output voltage waveform when a Composite Voltage Observer and a simple Current Observer are used.

5. Resource Utilization in FPGA

The realization of the control schemes has been done using DSP builder software in MATLAB simulink environment. DSP Builder tool provides a seamless design flow of algorithmic design and system-level integration in MATLAB and Simulink software and then ports the design to HDL for use in Altera's Quartus II design software. The DSP Builder can automatically generate preverified RTL output files—including an RTL design and testbench—from the Simulink software. The DSP Builder design flow for Altera FPGA is shown in Figure 26. Quartus II software has been used for fitting the synthesised algorithm into the FPGA. The resource utilization summary for both the control schemes has been shown in Table 3. The total logic elements needed to implement the composite observer scheme using Cyclone II is only about 66%. Table 4 indicates the resources utilized by both the observers in Cyclone II.

tab3
Table 3: Resource utilization of the Simple Observer (SO) and Composite Observer (CO) Control scheme using Quartus II tool.
tab4
Table 4: Resource utilization of the Simple Observer (SO) and Composite Observer (CO) using Quartus II tool.
512312.fig.0026
Figure 26: DSP Builder Design flow for Altera FPGAs.

6. Conclusion

The reduction of distortion in the voltage waveform in single phase Inverters, caused by the currents drawn by nonlinear loads, can be easily done by feeding back the instantaneous harmonic content of the voltage signal. This harmonic content is computed on-line by a composite observer in the voltage loop, which incidentally can also be used for obtaining the fundamental voltage signal for keeping the output voltage at the desired level. A simple Luenberger observer in the inner current loop serves the purpose of estimating the fundamental component of the load current, which is used for enhancing the stability of the overall scheme. Since the traditional trajectory control systems give rise to a steady-state error, the D-Q control procedure which is popular in 3-phase Inverters has been employed after suitable modifications for accurate voltage control of single-phase inverters. The local harmonic feedback gives rise to an enormous improvement in the quality of the waveform.

Interestingly the individual subblocks described in the work can be easily implemented in a Cyclone II FPGA, after trials in the Simulink environment. The composite observer has a parallel structure, which makes it desirable for implementation via the FPGA route. The digital multiply and add blocks were used for implementing the Park transform blocks. The various signals are almost simultaneously processed as if in an analog circuit, enabling a larger bandwidth for the control scheme. The total number of multipliers, adders, counters, integrators, and lookup tables was sufficient for implementing the inverter control system along with harmonic compensation procedure. Essentially, the harmonic distortion was cancelled by generating an equivalent opposing signal and adding it to the conventionally generated control signal within the FPGA. This procedure may be thought of as software-series compensation, which eliminates the need for external series transformers. It was found in the simulation and experimental studies that the composite observer shows a slightly faster response and purer output voltage waveform than a basic (simple) observer for the same feedback gain “”. Since the scheme works on the principle of “series software harmonic compensation,” which is effectively carried out at the input terminal of the PWM block, a reduction in the maximum available sinusoidal peak voltage results. This is not a serious deficiency, since the output transformer turns ratio can be slightly increased, even at the design stage. Most importantly, the entire scheme could be embedded into a single cyclone FPGA Chip without any additional RAM elements. Some left over area in the FPGA can be used for protection of the Inverter under fault conditions.

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