- About this Journal
- Abstracting and Indexing
- Aims and Scope
- Article Processing Charges
- Articles in Press
- Author Guidelines
- Bibliographic Information
- Citations to this Journal
- Contact Information
- Editorial Board
- Editorial Workflow
- Free eTOC Alerts
- Publication Ethics
- Reviewers Acknowledgment
- Submit a Manuscript
- Subscription Information
- Table of Contents
Volume 2010 (2010), Article ID 538454, 2 pages
Selected Papers from the Midwest Symposiumon Circuits and Systems
1Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN 37996-2100, USA
2Oak Ridge National Laboratory, Oak Ridge, TN 37831-6006, USA
Received 7 April 2010; Accepted 7 April 2010
Copyright © 2010 Gregory D. Peterson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This special issue of the VLSI Design journal is dedicated to the 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), held in August 2008 at Knoxville, Tennessee. The papers at MWSCAS spanned a broad spectrum of topics including theory, CAD, digital systems, and emerging technologies.
A number of quality papers in theory and CAD were submitted to this special issue. For example, nonlinear signal processing enables improved performance and power usage, but requires analog circuitry for practical systems. Odame and Hasler explore techniques for representing nonlinear circuit behavior in their paper Nonlinear circuit analysis via perturbation methods and hardware prototyping.
Zhu et al. explore a novel capacitor array structure with theoretic and simulation studies to develop a Successive Approximation Register for use with converters in Linearity analysis on a series-split capacitor array for high-speed SAR ADCs.
The paper from Reza Hashemanian presents a new approach for biasing analog circuits. The technique begins with localized optimization of nonlinear components at their operating points before turning to global optimization including the use of fixators and norators.
The paper Error immune logic for low power probabilistic computing from Marr et al. presents theorems related to constructing datapath circuits that yield an increased immunity to noise and can be applied to develop ultra-low power datapath circuits.
The paper by Yelamarthi and Chen presents an algorithm for timing optimization of CMOS dynamic logic along with a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic.
Achieving timing closure looms as a major challenge in taping out a design. In Post-CTS delay insertion, Lu and Taskin explore techniques for improving clock performance by developing an optimization approach for implementing clock skew scheduling on circuits after clock tree synthesis is complete.
A number of digital circuits and systems were presented at MWSCAS. In A low power digitally controlled oscillator for all digital phase locked loops, Zhao and Kim present a low power and low jitter 12-bit CMOS digitally controlled oscillator. This DCO is a key component of their all-digital PLL that helps achieve faster acquisition times with low power and jitter.
Sumathi and Janakiraman present FPGA implementation of an amplitude modulated continuous wave ultrasonic ranger using restructured phase locking scheme that discusses a design for an accurate ultrasonic range finder with a restructured phase-locked loop employing a Sliding Discrete Fourier Transform.
Industrial applications of Reconfigurable computing to power systems exploit the FPGA####^~^~^~^~^~^####x2019;s flexibility and performance. Selvajyothi and Janakiraman discuss their design for using an FPGA to control a single phase inverter.
In Evolvable block-based neural network design for applications in dynamic environments, Merchant and Peterson explore the use of reconfigurable computing to implement embedded neural network structures that are optimized during execution through the use of genetic algorithms.
Pseudorandom number generation represents one of the more expensive computational tasks commonly required for scientific computing, cryptography, simulation, and even gaming algorithms. Lee et al. present a hardware-accelerated implementation of a scalable parallel library of pseudo-random number generators.
In A pipelined and parallel architecture for quantum monte carlo simulations on FPGAs, Gothandaraman et al. present a parameterized framework for supporting computational chemistry research on high performance reconfigurable computing platforms.
The MWSCAS papers also include emerging technologies and novel applications. Ulaganathan et al. discuss the implementation of an extreme environment circuit for data acquisition in A SiGe BiCMOS instrumentation channel for extreme environment applications.
The emerging technology of carbon nanotubes promise useful characteristics for devices or wires. Xu et al. explore these topics in Emerging carbon nanotube electronic circuits, modeling and performance.
The authors would like to conclude this Editorial by thanking our Editor in Chief, Dr. Saeid Nooshabadi for his support in the publication of this Special Issue. They would also like to express our gratitude for the excellent help and advice of the reviewers. They diligently read the submissions, provided invaluable feedback to the paper authors, and helped us to select the highest quality papers.
Gregory D. Peterson