VLSI Design
Volume 2010 (2010), Article ID 946710, 11 pages
doi:10.1155/2010/946710
Research Article

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Jun Zhao and Yong-Bin Kim

Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA

Received 31 May 2009; Accepted 20 October 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 Jun Zhao and Yong-Bin Kim. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. I. Hwang, S. Lee, S. Lee, and S. Kim, “A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application,” in Proceedings of the 47th Annual IEEE International Solid-State Circuits Conference (ISSCC '00), pp. 168–169, San Francisco, Calif, USA, February 2000. View at Scopus
  2. D. W. Boerstler, “Low-jitter PLL clock generator for microprocessors with lock range of 340–612 MHz,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 513–519, 1999. View at Publisher · View at Google Scholar · View at Scopus
  3. V. R. von Kaenel, “A high-speed, low-power clock generator for a microprocessor application,” IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp. 1634–1639, 1998. View at Scopus
  4. P. Larsson, “A 2–166 MHz 1.2–2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '99), pp. 356–357, San Francisco, Calif, USA, February 1999. View at Publisher · View at Google Scholar
  5. I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599–1607, 1992. View at Publisher · View at Google Scholar · View at Scopus
  6. C.-C. Chung and C.-Y. Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 347–351, 2003. View at Publisher · View at Google Scholar · View at Scopus
  7. P. Nilsson and M. Torkelson, “A monolithic digital clock-generator for on-chip clocking of custom DSP's,” IEEE Journal of Solid-State Circuits, vol. 31, no. 5, pp. 700–706, 1996. View at Scopus
  8. R. B. Staszewski and P. T. Balsara, “Phase-domain all-digital phase-locked loop,” IEEE Transactions on Circuits and Systems II, vol. 52, no. 3, pp. 159–163, 2005. View at Publisher · View at Google Scholar · View at Scopus
  9. M. Saint-Laurent and G. P. Muyshondt, “A digitally controlled oscillator constructed using adjustable resistors,” in Proceedings of IEEE Southwest Symposium on Mixed-Signal Design, pp. 80–82, Austin, Tex, USA, February 2001.
  10. P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and B. Haroun, “A robust digital delay line architecture in a 0.13 μm CMOS technology node for reduced design and process sensitivities,” in Proceedings of the International Symposium on Quality Electronic Design (ISQED '02), pp. 148–153, San Jose, Calif, USA, March 2002.
  11. T. Olsson and P. Nilsson, “A digitally controlled pll for SoC applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 751–760, 2004. View at Publisher · View at Google Scholar · View at Scopus
  12. R. B. Staszewski, J. Wallberg, S. Rezeq, et al., “All-digital PLL and GSM/EDGE transmitter in 90 nm CMOS,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '05), pp. 316–317, San Francisco, Calif, USA, February 2005. View at Scopus
  13. J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital phase-locked loop with 50-cycle lock time suitable for highperformance microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412–422, 1995. View at Publisher · View at Google Scholar
  14. I.-C. Hwang, S.-H. Song, and S.-W. Kim, “A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1574–1581, 2001. View at Publisher · View at Google Scholar · View at Scopus
  15. J. Zhao and Y.-B. Kim, “A 12-bit digitally controlled oscillator with low power consumption,” in Proceedings of the 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '08), pp. 370–373, Knoxville, Tenn, USA, August 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A portable digitally controlled oscillator using novel varactors,” IEEE Transactions on Circuits and Systems II, vol. 52, no. 5, pp. 233–237, 2005. View at Publisher · View at Google Scholar · View at Scopus
  17. E. Roth, M. Thalmann, N. Felber, and W. Fichtner, “A delay-line based DCO for multimedia applications using digital standard cells only,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '03), vol. 1, pp. 432–505, San Francisco, Calif, USA, February 2003. View at Publisher · View at Google Scholar · View at Scopus