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VLSI Design
Volume 2011 (2011), Article ID 845957, 13 pages
http://dx.doi.org/10.1155/2011/845957
Research Article

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Department of Electric Engineering, Technion, Israel Institute of Technology, Haifa 32000, Israel

Received 23 September 2010; Accepted 28 January 2011

Academic Editor: Shiyan Hu

Copyright © 2011 Yoni Aizik and Avinoam Kolodny. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.