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Volume 2011 (2011), Article ID 845957, 13 pages
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
Department of Electric Engineering, Technion, Israel Institute of Technology, Haifa 32000, Israel
Received 23 September 2010; Accepted 28 January 2011
Academic Editor: Shiyan Hu
Copyright © 2011 Yoni Aizik and Avinoam Kolodny. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- I. E. Sutherland, R. F. Sproull, and D. F. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kauffmann, Boston, Mass, USA, 1999.
- P. I. Penzes and A. J. Martin, “Energy-delay efficiency of VLSI computations,” in Proceedings of the 12th ACM Great Lakes symposium on VLSI (GLSVLSI '02), April 2002.
- V. Zyuban and P. N. Strenski, “Balancing hardware intensity in microprocessor pipelines,” IBM Journal of Research and Development, vol. 47, no. 5-6, pp. 585–598, 2003.
- V. Zyuban and P. Strenski, “Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels,” in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 166–171, Monterey, Calif, USA, August 2002.
- D. Marković, V. Stojanović, B. Nikolić, M. A. Horowitz, and R. W. Brodersen, “Methods for true energy-performance optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282–1293, 2004.
- C. P. Chen, C. C. N. Chu, and D. F. Wong, “Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 7, pp. 1014–1025, 1999.
- R. Gonzalez, B. M. Gordon, and M. A. Horowitz, “Supply and threshold voltage scaling for low power CMOS,” IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210–1216, 1997.
- Z. Chen, M. Johnson, L. Wei, and K. Roy, “Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks,” in Proceedings of the International Symposium on Low Power Design, pp. 239–244, 1998.
- L. Benini, G. de Micheli, and E. Macii, “Designing low-power circuits: practical recipes,” IEEE Circuits and Systems Magazine, vol. 1, no. 1, pp. 6–25, 2001.
- V. Khandelwal and A. Srivastava, “Leakage control through fine-grained placement and sizing of sleep transistors,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD '04), pp. 533–536, 2004.
- S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Springer, New York, NY, USA, 1998.
- R. Zlatanovici and B. Nikolić, “Power—performance optimization for custom digital circuits,” in Proceedings of the Power—Performance Optimization for Custom Digital Circuits (PATMOS '05), vol. 3728 of Lecture Notes in Computer Science, pp. 404–414, 2005.
- H. Q. Dao, B. R. Zeydel, and V. G. Oklobdzija, “Energy optimization of pipelined digital systems using circuit sizing and supply scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 2, pp. 122–134, 2006.
- V. Oklobdzija and R. K. Krishnamurthy, High-Performance Energy-Efficient Microprocessor Design, Springer, New York, NY, USA, 2006.
- A. Naveh, E. Rotem, A. Mendelson, et al., “Power and thermal management in the Intel core duo processor,” Intel Technology Journal, vol. 10, no. 2, 2006.
- AMD Press Release, “AMD Phenom X4 9100e processor enables full featured, sleek and quiet quad-core PCs,” AMD Press Resources Web Page, March 2008.
- H. Rahman and C. Chakrabarti, “A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage,” in Proceedings of the IEEE International Symposium on Cirquits and Systems (ISCAS '04), pp. 297–300, May 2004.
- Y. Xu, Z. Luo, and X. Li, “A maximum total leakage current estimation method,” in Proceedings of the IEEE International Symposium on Cirquits and Systems (ISCAS '04), pp. 757–760, May 2004.
- S. Boyd, Lieven Vandenberghe Convex Optimization, Cambridge University Press, Cambridge, UK, 2006.
- S. Boyd, S. J. Kim, L. Vandenberghe, and A. Hassibi, “A Tutorial on Geometric Programming,” Revised for Optimization and Engineering, July 2005.
- S. P. Boyd, S. J. Kim, D. D. Patil, and M. A. Horowitz, “Digital circuit optimization via geometric programming,” Operations Research, vol. 53, no. 6, pp. 899–932, 2005.
- A. Mutapcic, K. Koh, S. Kim, L. Vanden-Berghe, and S. Boyd, “GGPLAB: A Simple Matlab Toolbox for Geometric Programming,” May 2006, http://www.stanford.edu/boyd/ggplab/.
- “International Technology Roadmap for Semiconductors,” 2007 Edition, http://www.itrs.net/Links/2007ITRS/Home2007.htm.
- A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of average switching activity in combinational and sequential circuits,” in Proceedings of the 29th ACM/IEEE Conference on Design Automation, pp. 253–259, Anaheim, Calif, USA, June 1992.