VLSI Design

Research Article

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Algorithm 2

Algorithm for constructing an -sided semi-universal switch block of size .
Algorithm: Semi-universal .
Input: —number of sides of the polygonal switch block; —number of
terminals on each side of the polygonal switch block, .
Output: ; : set of terminals; : set of switches.
(1)   Let internal terminals ,
   and
   ,
  where for .
(2)   ;
(3)   for     to     do
(4)     for     to     do
(5)       for     to     do
(6)         ;
(7)   for     to     do
(8)     for     to     do
(9)       for     to     do
(10)         ;
(11)   Return