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VLSI Design

Volume 2013 (2013), Article ID 103473, 15 pages

http://dx.doi.org/10.1155/2013/103473

## A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

^{1}Department of Computer Science and Information Engineering, National Taiwan Ocean University, 2 Pei-Ning Road, Keelung 202-24, Taiwan^{2}Department of Electronic Engineering, National Ilan University, 1, Sec. 1, Shen-Lung Road, I-Lan 260, Taiwan^{3}Department of Electronic Engineering, China University of Science and Technology, 245, Sec. 3, Academia Road, Nangang District, Taipei City 115, Taiwan

Received 5 August 2013; Accepted 27 September 2013

Academic Editor: Wen-Jyi Hwang

Copyright © 2013 Mao-Hsu Yen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a generic three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of a polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx 4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the three-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize the number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved. Based on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.

#### 1. Introduction

Field Programmable Gate Arrays (FPGA’s) [1, 2] are now widely used for the implementation of digital circuits and many commercial products. A typical symmetric FPGA, consisting of an array of logic blocks (Ls) that can be connected by general routing resources, is shown in Figure 1. The routing resources comprise segments of wires and two kinds of blocks, switch blocks (SBs), and connection blocks (CBs). Both the switch and connection blocks contain many programmable switches. The input and output pins of a logic block are connected to its surrounding connection blocks, which in turn are connected to the switch blocks. An arbitrary digital circuit is divided into several parts such that each part is realized by a logic block; then these logic blocks are interconnected by routing resources in an FPGA.

Since the programmable switches usually have high resistance and capacitance and occupy a large area, the number of programmable switches used in an FPGA affects its speed performance, die size, and routability. The time delay along an interconnection path is significant and often exceeds the delay of logic blocks. The routing area of FPGA typically takes from 70 to 90% of the total area [3]. Intuitively, increasing the number of programmable switches of routing network in an FPGA deliver good routability. However, routing network with fewer programmable switches can reduce the impedance of interconnecting paths, and the overall interconnecting speed of the FPGA can thus be improved.

We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnect by a three-stage three-sided rearrangeable polygonal switching network. Figure 2 shows a model of polygonal FPGA, which consists of many clusters of logic block and pins interconnected by a three-stage three-sided polygonal switching network. The polygonal switching network is a three-stage three-sided switching network for connecting inputs of logic-block (), outputs of logic-block (), and pins () to interconnect each other. A 3-sided switch network means that we have three disjoint sets (, , and ) of terminals to be connected. Furthermore, in the 3-stage switching network, the longest connection of terminals is the length passing through 3 switches. Through the arrangement of switches (or interconnects) in various combinations, a terminal in one set can be connected to a terminal in any other set. Assuming that all *connections* are point-to-point connections, the enumeration of any pair of the above three sets of terminals to be connected is called an *assignment*, where a terminal of the three sets can appear in at most one pair. An assignment for a network is *realizable* if there exist in the network disjoint paths connecting every pair of terminals given in the assignment. A 3-sided switching network is *rearrangeable* [4–8] if any given assignment is realizable. Since a *rearrangeable* switching network has better capability to accomplish a given *assignment*, we focus on the design of a *rearrangeable* 3-sided switching network for the interconnection of terminals in a PFPGA.

Studies on multistage switching networks are fruitful. Yen and Feng [5] proposed a class of -stage two-sided networks, which are equivalent to Benes networks. All networks in this class are nonblocking and rearrangeable. The one-stage one-sided rearrangeable switching networks have been discussed by Mitchell and Wild [6]; then, the reduction of crosspoints in the one-stage one-sided crosspoint switching network has been investigated by Varma and Chalasani [7]. Gordon and Srikanthan [8] studied another multistage one-sided switching network with many switch elements. Chang et al. and Shyu et al. [9–11] proposed universal switch blocks that can improve the routability in a Xilinx 4000-like (clique-based) FPGAs routing network. Fan et al. [12] designed and proved a class of optimum Polygonal Switch Block PSB for all even and . Yen et al. [13] proposed rearrangeable switch network that can improve the routability for a binary fat tree. However, most of the studies are concerned with either the two-sided rearrangeable switching networks or the one-stage one-sided rearrangeable switching networks. As well as, in terms of the number of switches, the one-sided or two-sided switching network is not efficient for interconnecting the three disjoint sets of terminals. Thus, this paper presents a generic three-stage three-sided rearrangeable switching network for Polygonal Field Programmable Gate Array by using Polygonal Switching Blocks (PSBs) [14–16] and crossbars. We investigate how to use PSBs to construct a rearrangeable 3-sided Polygonal switching network (PSN) and how to minimize the number of switches repaired. We also compare our PSN with a three-stage 3-sided clique-based (Xilinx 4000-like FPGAs) polygonal switching network of the same size and with the same number of switches and derive that the three-stage 3-sided clique-based polygonal switching network is not rearrangeable.

The next section gives a description on our polygonal FPGA model, 3-sided polygonal switching network, and some notations and definitions. In Section 3, we prove that our 3-sided switching polygonal network is rearrangeable, while Section 4 shows how we minimize the number of switches in a rearrangeable PSN. In Section 5, we propose a polygonal field programmable gate array that consists of many logic blocks interconnected by a PSN. Conclusions are reported in Section 6.

#### 2. Polygonal Field Programmable Gate Array

Figure 2 shows a model of polygonal FPGA, which consists of many clusters of logic block and pins interconnected by a generic three-sided Polygonal Switching Network. In this study, we investigate the logic block based on a cluster of 4-input look-up tables (LUTs). The reason is that most research has focused on LUT-based logic blocks, and Rose et al. [17] showed that a 4-input LUT is the most area-efficient LUT. The three-sided polygonal switching network consists of connection blocks (CBs) and an -sided polygonal switch block (PSB). Each connection block is connected to one of the sides of the polygonal switch block. All the above blocks contain many programmable switches. The polygonal switching network is a three-stage three-sided switching network for connecting inputs of logic-block, outputs of logic-block, and pins to interconnect each other. First, the input and output pins of cluster-based logic blocks and pins are connected to the related connection blocks (CBs), which are then interconnected by a polygonal switch block. That is, the first and third stages consist of CBs, and the second stage is a PSB with sides. In this PFPGA, any two terminals of the three groups in a PFPGA can be connected with fewer than three switches. Thus, the speed performance of a PFPGA can be improved.

Since routing area in an FPGA is typically more than the active area, so we investigate how to use PSBs to construct a rearrangeable 3-sided Polygonal Switching Network (PSN) and how to minimize the number of switches repaired in the following section. We also compare our PSN with a three-stage 3-sided clique-based polygonal switching network of the same size and with the same number of switches and derive that the three-stage 3-sided clique-based polygonal switching network is not rearrangeable.

##### 2.1. Three-Sided Polygonal Switching Network

The proposed generic three-stage 3-sided polygonal switching network (PSN) can be used to interconnect terminals in pairs of the three disjoint sets (, , and ). This PSN consists of crossbars (CBs) interconnected by a -side polygonal switch block (PSB). Figure 3(a) shows an example of PSN, where the first and third stages are composed of 8 CBs; and the second (internal) stage is a PSB with 8 sides.

As shown in Figure 3(b), each crossbar in a PSN, denoted as for , is an block architecture, where is the number of external terminals connected to one of the three sets and is the number of internal terminals connected to one side of PSB, [12]. We classify connection blocks under three groups: , , and , which are used to connect the inputs and outputs of logic-blocks and pins, respectively. Denote that , , , , , , , , , , , , where , , and are the number of in the , , and , respectively. As shown in Figure 2, the pins are connected to = , and inputs and outputs of logic-blocks are connected to , , , and , , respectively. Therefore, a three-sided polygonal switching network should provide , , and external terminals to connect the inputs and outputs of logic-block and pins, respectively.

We label these external and internal terminals on a as , , , and , , , , respectively. We represent the external terminals of a ( terminals), (output terminals), and (input terminals). Similarly, the internal terminals are denoted as , , and . In total, we have two sets of terminals: the external terminal set and the internal terminal set in a PSN. Furthermore, the set of , , and have , , and external terminals, respectively. Similarly, the set of , , and have , , and internal terminals on crossbars. For example, Figure 3(a) shows a 3-sided switching network PSN with , , and , where , ; and with , , and , where , . Any pair of external terminals from two sets of , , and can be connected to each other by using a 3-sided switching network PSN, but no pair external terminals from the same set can be interconnected.

Through the programmable and electrically noninteracting switches in a crossbar , every external terminal in can be connected to a free internal terminal in without any blocking. For example, if switch SW is programmed to be “ON”, then connection between an external terminal and an internal terminal is established, where , , and . Figure 3(b) shows a routing example, where is connected to by programming SW, and this routing solution is illustrated by thick lines. In such a way, an external terminal can be connected to an internal terminal by programming one switch in a .

The polygonal switch block in a PSN, denoted as a PSB, is an -side switch block with internal terminals on each side of the block, as shown in Figures 4(a) and 5(a). Label the terminals on the th side of a PSB as for . Remember that internal terminals , where , , and . If a switch SW exists in PSB and is programmed to be “ON”, then a connection between terminals and is established, where and belong to two different sets of , , and . To form a 3-sided switching network PSN we need crossbars connected to a polygonal switch block PSB. Thus, a 3-sided switching network can be completely characterized by five parameters: , and , and denoted as PSN, for , , , , , and . For example, Figure 3(a) shows a PSN with , , , , and .

As shown in Figures 4(a) and 5(a), we will study the 3-sided switching network with two different topologies of polygonal switch blocks in this paper, denoted as and , respectively. Algorithm 1 constructs a clique-based polygonal switch block . As shown in Figure 4, a is equivalent to isolated . In Figure 6 we show a 3-sided switching network, constructed with a . Algorithm 2 constructs the polygonal switch block . As shown in Figure 5, a is equivalent to isolated , . A 3-sided switching network consisting of crossbars connected to a is shown in Figure 7. Table 1 lists some symbols of 3-sided switching network specified in this paper.

Note that we do not allow any two external terminals from the same set of , , and to be interconnected in a PSN. Similarly, we do not allow any two internal terminals from the same set of , , and to be interconnected in a PSB. For example, Figures 4(a) and 5(a) show that and do not have any switches between the two sets of and from the same for the interconnection. That is, in either a (Figure 6) or a (Figure 7) no interconnections of external terminals from the same sets of and through or are allowed. In a or , since a terminal from a side in one set of , , and should be connected to any other terminal from the sides in the remaining two sets through switches, a polygonal switch block needs at least switches. Assume that both 3-sided switching networks and have the same size and the same number of switches. We will show that the three-stage 3-sided switching network with is rearrangeable and is even [12], but the with is not rearrangeable.

In a PSN, the *connection pair * is a point-to-point connection, where and belong to different sets of , , and . An assignment represents a set of connection pairs to be connected; thus each external terminal appears in at most one pair. A PSN switching network is *rearrangeable* if any assignment is *realizable* (*routable*).

Note that a connection pair belonging to is to be connected by passing through blocks . Given an on a PSB, each pair of connection is accomplished using terminals from two different sides of , , and ; we can thus classify these connections passing through a PSB into types of connections. Figure 8 shows the twenty possible types of connections in an eight-side switch block PSB. A *routing requirement vector * [9–11] for a PSB is a -tuple , , , , , , , , , , , , where represents the number of type- connections between and required to be connected through a PSB; for . In other words, is the number of connections in to be connected through the two sides and on a PSB, , where and belong to any two different sets of , , and . An RRV is said to be *realizable* (*routable*) on a PSB if there exist disjoint paths for on a PSB. Figure 8 shows an RRV = (, , , , , , , , , , , , , , , , , , , ) for PSB with eight sides.

For example, Figure 9(a) shows a routing instance with three nets corresponding to the RRV = (, 0, 0, 0, , 0, 0, 0, 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 0), and we try to route this RRV using the two different polygonal switch blocks and from Figures 4(a) and 5(b), respectively. As shown in Figures 9(b) and 9(c), however, there is always one net that cannot be routed on a . Thus, this RRV (, 0, 0, 0, , 0, 0, 0, 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 0) is not routable on a . Instances of the same RRV routable on a are shown in Figures 10(a) and 10(b), where the routing solutions are illustrated by thick lines.

Each connection pair is required to be connected by passing through in a PSN. Given an , we want to obtain an RRV , to be realized on a PSB, where is the number of the connection pairs required to be connected through PSB. For example, let = , , to be routed on a and a , which have been respectively shown in Figures 6 and 7. The RRV for the given on PSB is = (, 0, 0, 0, , 0, 0, 0, 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 0). We have already shown in Figures 10(a) or 10(b) that the RRV = (, 0, 0, 0, , 0, 0, 0, 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 0) can be routed on a . Since any external terminal in can be connected to a free internal terminal in without blocking through a crossbar , we show in Figures 11(a) and 11(b) two possible routing solutions for the given on a switching network. Instances in Figures 12(a) and 12(b) show that the same is not routable on a switching network, because the RRV = (, 0, 0, 0, , 0, 0, 0, 0, 0, 0, 0, 0, 0, , 0, 0, 0, 0, 0) contains at least one connection that cannot be routed on a as already shown in Figures 9(b) and 9(c). Therefore, we conclude a switch network constructed with a , where is not rearrangeable. In the following, we prove that a with is not rearrangeable.

Theorem 1. *A 3-sided switching network is not rearrangeable for , , , , , and .*

*Proof. *Observably, if a with is not rearrangeable, then a with is not rearrangeable. Thus, we need to prove that a is not rearrangeable.

Arbitrarily select three sides , , and of a , , we form an assignment , , , , , to be connected between the , , and on a . The RRV for routing on a is , as shown in Figure 4(a). Since a is equivalent to isolated ’s, the first can be realizable on isolated ’s, as shown in Figure 4(b). But, we cannot find enough disjoint paths to simultaneously realize an and an on the last , as shown in Figure 4(b). Thus, this cannot be realizable on a , because this RRV contains at least one connection that cannot be routed on a . Therefore, the is not rearrangeable.

In the following, we will explore the properties of the semiuniversal and polygonal switch block and show a switching network constructed with semiuniversal , where is rearrangeable.

##### 2.2. Semiuniversal and Polygonal Switch Blocks

Chang et al. and Shyu et al. [9–11] proposed a universal polygonal switch block to improve the routability in a Field Programmable Gate Array routing network. Fan et al. [12] designed and proved a class of optimum PSB for all even and . A is an -sided switch block with terminals on each side of the block; and a terminal from one side of can be interconnected to another terminal in the remaining sides. A polygonal switch block PSB is said to be *universal* [9–11] if any RRV , , , , , satisfying the following set of inequalities can be *realizable* on a PSB, for :
where for , and

Note that the number of connections interconnecting through each side of PSB cannot exceed ; this dimensional constraint [9–11] is characterized by the preceding inequalities, one for each side.

Label the terminals on the th side of a PSB as for . A generic *universal* switch block has been proposed by Shyu et al. [11]. As shown in Algorithm 3, the algorithm can be used to construct an -side universal switch block with terminals on each side. That is to say, any RRV satisfying the dimension constraint (i.e., the number of connections on each side of a PSB is at most ) is realizable on a , for and [12]. For example, Figure 13(b) shows a universal .

Since a semiuniversal in a does not allow any two internal terminals in the same set of , , and to be interconnected, where , , and , we have to modify Algorithm 3 to construct our . Algorithm 2 removes the switches SW, where and belong to the same set of , , and from , . For example, Figure 13(a) shows a *semiuniversal* switch block , which is equal to a universal in Figure 13(b) minus some prohibited switches in Figure 13(c). That is to say, a semiuniversal switch block contains a partial topology of the universal switch block .

In the following, we redefine the properties of the semiuniversal and polygonal switch block . A polygonal switch block PSB is said to be *Semiuniversal* (SU) if any RRV , ) satisfying the following set of inequalities is *realizable* on a PSB:
where , , for , and and belong to two different sets of , , and .

Note that the number of connections interconnecting through each side of PSB cannot exceed ; this dimensional constraint is characterized by the preceding inequalities, one for each side. Thus, the constructed by Algorithm 2 is semiuniversal. Also, any RRV satisfying the dimension constraint is simultaneously realizable on a .

#### 3. Rearrangeable 3-Sided Switching Networks

Since the programmable switches usually have high resistance and capacitance and occupy a large area, a rearrangeable 3-sided switching network PSN has routability and area efficiency. A 3-sided switching network can be constructed with crossbars and a semiuniversal . Based on the semiuniversality of a and the properties of a crossbar , we proceed to prove that the constructed PSN_{SU} is rearrangeable.

Theorem 2. *A 3-sided switching network , , , , is rearrangeable if and only if , , , , , and .*

*Proof. *Observably, if a , , , , with is rearrangeable, then a , , , , with is rearrangeable. Thus, we need to prove that a , , , , is rearrangeable, .

A is used to connect the external terminals of , , and to each other. Let ( terminals), (output terminals), and (input terminals), where on a , . The *connection pair * is a point-to-point connection, where and belong to different sets of , , and . An assignment represents a set of connection pairs to be connected; thus each external terminal appears in at most one pair. The is rearrangeable if any assignment is realizable.

(If) Any assignment can be connected on , since each connection pair is required to be connected by passing , we can obtain that this kind of RRV , , , , , , , , , , , , for any given to be realized on a , where represents the number of type- connections between and . Furthermore, this RRV satisfying the dimension constraint is realizable on a *semiuniversal *, due to the number of connection pairs in interconnecting through each side of does not exceed . Therefore, for each , we can find a connection path between and after the RRV has been realized on a , where . Then the connection is realizable by programmed three switches, one switch SW in the and two other switches SW and SW in the and , respectively. Therefore, any given assignment for a is realizable, because there exist in the disjoint paths connecting all the pairs of terminals given in the assignment . Thus, a switching networks with is rearrangeable.

(Only if) If in a with , we have an assignment , , , to be connected between the and on a , where and belong to different sets of , , and , since each connection pair is connected by passing blocks . In each , we cannot find enough disjoint paths to connect all the external terminals in to all the internal terminals in , which in turn are connected to the th side of a , due to . Thus, this is not realizable on a with .

#### 4. Minimize the Number of Switches

We have shown a rearrangeable 3-sided switching network in the above section. Now, we start to explore the effect of the parameters , and in a on the switch-efficiency, and we try to find proper , and values to minimize the number of switches needed in a rearrangeable to interconnect terminal pairs from the three sets of , , and . We assume that the set of , , and have , , and external terminals, respectively.

Since the number of switches in crossbars is equal to and the number of switches in a polygonal switch block is equal to , we denote the number of switches in a as . By summing the number of switches in all the above blocks, we have Substituting , , and into (4) results in Let and solve for , since , , and are constant, we have which implies

This indicates that the function has minimum value at ,

From (8), we have that a with contains the number of switches to a minimum. Given a interconnecting terminals pairs from , , and , where the set of , , and have , , and external terminals, respectively. Tables 2 and 3 show the number of switches needed in rearrangeable each of which varies with . In Table 2, the rearrangeable switching network with (from (8)) is the best choice for interconnecting terminals pairs from the three terminal sets in terms of the number of switches. Furthermore, in Table 3, the rearrangeable switching network with (from (8)) is the best choice for interconnecting terminals pairs from the three terminal sets.

#### 5. Polygonal FPGA

Figure 2 shows a model of polygonal FPGA (PFPGA), which consists of many clusters of logic block and pins interconnected by a three-sided polygonal switching network. In this study, we investigate the logic block based on a cluster of 4-input look-up tables (LUTs). The three-sided polygonal switching network consists of connection blocks (CBs) and an -sided polygonal switch block (PSB). Each connection block is connected to one of the sides of the polygonal switch block. All the above blocks contain many programmable switches. The polygonal switching network is a three-stage three-sided switching network [4] for connecting inputs of logic-block, outputs of logic-block, and pins to interconnect each other. First, the input and output pins of cluster-based logic blocks and pins are connected to the related connection blocks (CBs), which are then interconnected by a three-sided polygonal switch block (PSB). That is, the first and third stages consist of CBs and the second stage is a PSB with sides. In this PFPGA, any two terminals of the three groups in a PFPGA can be connected with fewer than three switches. Thus, the speed performance of a PFPGA can be improved.

Figure 14 shows that the basic logic block (BLB) [18] of our PFPGA has inputs and 1 output excluding the “global clock”. A BLB consists of a 4-input LUT and a register, and the BLB output can be either the registered or unregistered version of the LUT output. A BLB contains configurable digital circuits that can be used to implement different logic functions. As shown in Figure 15, the complete cluster-based logic block (CLB) is comprised of BLB, denoted as . A has inputs and outputs. Let on a ; then inputs of a are connected to one of , and outputs of ’s connected to one of . Let be the total number of BLB’s in a PFPGA with pins, as shown in Figure 2. We can obtain the following three parameters , , and for a PFPGA:

The key factors to the PFPGA switch-efficiency and speed-efficiency are the structure of its switching network structure and the granularity of its cluster-based logic blocks . That is to say, the parameters and in a PFPGA affect its speed performance, die size, and routability.

Cluster-based logic blocks have two other advantages over single BLB logic blocks. First, in an FPGA composed of logic clusters, many nets will be completely contained within a logic cluster. If these nets are routed using multiplexers within a cluster, the delay of these multiplexers is less than that of the main FPGA. Secondly, clustering BLB’s into one logic cluster will greatly reduce the placement time by a factor of , which is of increasing concern in today’s large FPGA’s.

##### 5.1. Number of Switches in a PSN_{SU}

Let be the total number of BLB’s in a PFPGA with pins, and a BLB has inputs and 1 output. The complete cluster-based logic block (CLB) is composed of BLB’s, denoted as . The number of switches in polygonal switching network is obtained as follows.

Because we have the following facts:(i)the number of switches in ’s is equal to ,(ii)the number of switches in a is equal to , where , , , , and , and , and are constants.

Denote the number of switches in a as . By summing the number of switches in all the above blocks, we have

From (10), is determined by the and values. In the following section, we will find proper values and to minimize the number of switches needed in a polygonal switching network through experiments.

##### 5.2. Experimental Results

To explore the effects of and values of a polygonal switching network on the switch-efficiency in a PFPGA with BLB’s and pins, we have implemented a maze router [19–21] in C language and executed the codes on an IBM System M3. We examine the effect of two parameters, and , on the switch performance using the CGE [1] and SEGA [22] benchmark circuits.

By routing different cluster size of logic blocks, the switch performance of a three-sided polygonal switching network was evaluated. From the results of a , as listed in Table 4, we first determine the minimum number of tracks required to complete the 100% routing of each circuit, using three-sided polygonal switching networks , , , , . Then we can find the , , , , value by substituting the values of , , , , and into (10).

Figure 16 shows that the numbers of programmable switches used in the 14 benchmarks vary with , where . Experimental results demonstrate that the switches number used in PSN_{SU} is minimum for a PFPGA with (for CGE) and (for SEGA), respectively. We assume that the available pin count of a PFPGA is and the number of BLB is about 208. Therefore, our PFPGA consists of 52 and pins interconnected by a three-sided polygonal switching network , , , , .

##### 5.3. VLSI Chip Implementation of the PFPGA

The chip layout of our PFPGA using a 0.18 *μ*m CMOS technology is shown in Figure 17. The polygonal switching network area of a PFPGA is 1255 *μ*m × 1350 *μ*m. And the total area of this PFPGA is 1550 *μ*m × 1600 *μ*m. So we can calculate the ratio of routing area to total area to be 68.81%. Since routing area typically takes 70–90 percent of the total chip area in general FPGA [3]. So we conclude that the polygonal FPGA gets more area utilization.

In our proposed PFPGA architecture, we provide a three-stage routing resources concept. The first and third stages of routing are the connection blocks in two CLBs, which can meet local signal routing requirements. And the second layer of routing is the polygonal switch block, which is used to connect any output signal of a CLB to any input signal of a CLB. Thus, the longest distance in our PFPGA is only three stages. The maximum point-to-point of PSN_{SU} delay is 13 ns. So we conclude that the architecture of PFPGA has better speed improvement. As mentioned above, this chip architecture uses less number of programmable switches and the speed performance of a PFPGA can be achieved. Thus, it is very suitable for VLSI implementation.

#### 6. Conclusions

This paper first proposed a generic three-stage and rearrangeable three-sided switching network used in the PFPGA for all even . The PSN consists of crossbars interconnected by a semiuniversal polygonal switch block with sides. We not only provide the designers with a rearrangeable with for connecting terminal pairs from three disjoint terminal sets to each other but also determinate the important parameter to minimize the number of switches needed in that network. We also propose a PFPGA that consists of many logic blocks interconnected by a PSN_{SU}. We investigate the effect of the PSN_{SU} structure and the granularity of its interconnecting cluster-based logic blocks on the switch-efficiency and speed-efficiency performance. Experimental results demonstrate that the switch-efficiency and speed-efficiency are improved so it holds promise as a practical PFPGA with polygonal switching network.

#### Acknowledgment

This work was partly supported by the National Science Council, Taiwan, under Grant NSC 101-2221-E-019-071.

#### References

- J. Rose and S. Brown, “Flexibility of interconnection structures for field-programmable gate arrays,”
*IEEE Journal of Solid-State Circuits*, vol. 26, no. 3, pp. 277–282, 1991. View at Publisher · View at Google Scholar · View at Scopus - S. Franchini, A. Gentile, F. Sorbello, G. Vassallo, and S. Vitabile, “An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support,”
*Integration, the VLSI Journal*, vol. 42, no. 3, pp. 346–355, 2009. View at Publisher · View at Google Scholar · View at Scopus - S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic,
*Field-Programmable Gate Arrays*, Kluwer Academic, 1992. - V. E. Benes, “On rearrangeable three-stage connecting networks,”
*Bell System Technical Journal*, vol. 41, no. 5, pp. 1481–1492, 1962. - Y. M. Yen and T. Y. Feng, “On a class of rearrangeable networks,”
*IEEE Transactions on Computers*, vol. 41, no. 11, pp. 1361–1379, 1992. View at Publisher · View at Google Scholar - C. Mitchell and P. Wild, “One-stage one-sided rearrangeable switching networks,”
*IEEE Transactions on Communications*, vol. 37, no. 1, pp. 52–56, 1989. View at Scopus - A. Varma and S. Chalasani, “Reduction of crosspoints in one-sided crosspoint switching networks,” in
*Proceedings of the 8th Annual Conference of the IEEE Computer and Communications Societies. Technology: Emerging or Converging? (INFOCOM '89)*, vol. 3, pp. 943–952, Ottawa, Canada, April 1989. View at Scopus - J. Gordon and S. Srikanthan, “Single sided switching networks,”
*Electronics Letters*, vol. 26, no. 4, pp. 248–250, 1990. View at Scopus - Y.-W. Chang, D. F. Wong, and C. K. Wong, “Universal switch modules for fpga design,”
*ACM Transactions on Design Automation of Electronic Systems*, vol. 1, no. 1, pp. 80–101, 1996. View at Scopus - G. M. Wu, M. Shyu, and Y. -W. Chang, “Universal switch blocks for three-dimensional FPGA design,” in
*Proceedings of the ACM International Symposium on Field Programmable Gate Arrays (FPGA '99)*, Monterey, Calif, USA, February 1999. - M. Shyu, G.-M. Wu, Y.-D. Chang, and Y.-W. Chang, “Generic universal switch blocks,”
*IEEE Transactions on Computers*, vol. 49, no. 4, pp. 348–359, 2000. View at Publisher · View at Google Scholar · View at Scopus - H. Fan, J. Liu, Y.-L. Wu, and C. K. Wong, “Reduction design for generic universal switch blocks,”
*ACM Transactions on Design Automation of Electronic Systems*, vol. 7, no. 4, pp. 526–546, 2002. View at Publisher · View at Google Scholar · View at Scopus - M.-H. Yen, C. Yu, H.-Y. Shin, and S.-J. Chen, “A three-sided rearrangeable switching network for a binary fat tree,”
*International Journal of Electronics*, vol. 98, no. 6, pp. 713–734, 2011. View at Publisher · View at Google Scholar · View at Scopus - M. H. Yen, M. C. Shie, and S. H. Lan, “Polygonal routing network for FPGA/FPIC,” in
*Proceedings of the International Symposium on VLSI Technology, System, and Applications (VLSI-TSA '99)*, pp. 104–107, 1999. - M.-H. Yen, S.-J. Chen, and S. H. Lan, “Symmetric and programmable multi-chip module for low-power prototyping system,”
*VLSI Design*, vol. 12, no. 2, pp. 113–124, 2001. View at Scopus - M.-H. Yen, S.-J. Chen, and S. H. Lan, “A three-stage one-sided rearrangeable polygonal switching network,”
*IEEE Transactions on Computers*, vol. 50, no. 11, pp. 1291–1294, 2001. View at Publisher · View at Google Scholar · View at Scopus - J. Rose, R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency,”
*IEEE Journal of Solid-State Circuits*, vol. 25, no. 5, pp. 1217–1225, 1990. View at Publisher · View at Google Scholar · View at Scopus - V. Betz and J. Rose, “Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size,” in
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '97)*, pp. 551–554, Santa Clara, Calif, USA, May 1997. View at Scopus - M. Marek-Sadowska, “Switch box routing: a retrospective,”
*Integration, the VLSI Journal*, vol. 13, no. 1, pp. 39–65, 1992. View at Scopus - W. K. Luk, “A greedy switch-box router,”
*Integration, the VLSI Journal*, vol. 3, no. 2, pp. 129–149, 1985. View at Scopus - J. Pan, Y.-L. Wu, C. K. Wong, and G. Yan, “On the optimal four-way switch box routing structures of FPGA greedy routing architectures,”
*Integration, the VLSI Journal*, vol. 25, no. 2, pp. 137–159, 1998. View at Scopus - G. G. Lemienx and S. D. Brown, “A detailed routing algorithm for allocating wire segments in field-programmable gate arrays,” in
*Proceedings of the ACM/SIGDA Physical Design Workshop*, pp. 215–216, Lake Arrowhead, Calif, USA, 1993.