A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Algorithm 3

Algorithm for constructing an 𝑆-sided universal switch block of size 𝑚.

Algorithm: Universal switch block PSB_𝑈(𝑚,𝑆,𝒯,SW).

Input: 𝑆=𝑠_𝑝+𝑠_𝑜+𝑠_𝑖—number of sides of the polygonal switch block; 𝑚—number of

terminals on each side of the polygonal switch block, 𝑚∈even.

Output: (𝒯,SW); 𝒯: set of terminals; SW: set of switches.

(1)   𝒯←𝑡_𝑖,𝑗,∀𝑖=1,2,…,𝑆,∀𝑗=1,2,…,𝑚;

(2)  SW←∅;

(3)   for  𝑖=1  to  𝑆−1  do

(4)     for  𝑘=𝑖+1  to  𝑆  do

(5)       for  𝑗=1  to  𝑚  do

(6)        SW←SW∪𝑡_𝑖,𝑗,𝑡_{𝑘,𝑚−𝑗+1};

(7)  Return  (𝒯,SW)