A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Figure 5

A polygonal switch block PSB_SU(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚=4, 𝑠_𝑝=2, 𝑠_𝑜=2, and 𝑠_𝑖=4. (b) Its correspondence to two PSB_SU(2,2,2,4).