A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Table 4

Minimum number of tracks and switches needed for detailed-routing completion for CLB(5).

Circuit	LBs	#Con.	PSNSU(𝑛,𝑚,𝑠𝑖,𝑠𝑜,𝑠𝑝)
			𝑚	𝑠𝑖	𝑠𝑜	𝑠𝑝	SWSU
BUSC	24×22	392	22	22	6	4	9064
DMA	34×30	771	24	45	11	2	14358
DFSM	44×42	1422	27	84	20	3	30690
BNRE	42×40	1257	27	76	19	4	29517
Z03	52×50	2135	27	120	29	3	42894
9symml	20×18	259	22	15	4	1	4428
alu2	28×24	511	23	29	7	1	8007
alu4	36×32	851	27	51	13	2	17235
apex7	22×18	300	22	16	4	5	7988
example2	26×22	444	23	24	6	8	13122
k2	42×38	1256	25	72	18	5	28050
term1	18×16	202	22	12	3	3	5100
too_large	28×26	519	22	32	8	3	11004
vda	32×30	722	25	42	10	3	14750
Total	—	—	—	—	—	—	236207