Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

Table 2

Comparison between ZBB, DTMOS, and GLBB schemes at nominal conditions (TT process corner, = 0.3 V, and = 27°C).

	ZBB	DTMOS	GLBB
Silicon area [µm^2]	20.7	123.2	60.5
Delay [µs]	0.70	0.78	0.59
Leakage current [nA]	0.20	0.24	0.21
Energy per operation; ( = 80 FO4, = 0.2) [fJ]	0.75	2.27	0.57