The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45&#x2009;nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.

Ramiro Taco

Marco Lanuzza

Domenico Albano

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90&#x2009;nm and 180&#x2009;nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent&#x2019;s Advanced Design Systems (ADS) software.

David H. K. Hoe

Xiaoyu Jin

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8&#x2009;<i>&#x3bc;</i>W. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30&#x2009;<i>&#x3bc;</i>m &#xd7; 30&#x2009;<i>&#x3bc;</i>m, resulting in that the integration capacitor should be selected as 0.74&#x2009;pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1&#x2009;<i>&#x3bc;</i>V. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix.

Xiao Wang

Zelin Shi

Baoshu Xu

A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

Ultrasound imaging is one of the available imaging techniques used for diagnosis of kidney abnormalities, which may be like change in shape and position and swelling of limb; there are also other Kidney abnormalities such as formation of stones, cysts, blockage of urine, congenital anomalies, and cancerous cells. During surgical processes it is vital to recognize the true and precise location of kidney stone. The detection of kidney stones using ultrasound imaging is a highly challenging task as they are of low contrast and contain speckle noise. This challenge is overcome by employing suitable image processing techniques. The ultrasound image is first preprocessed to get rid of speckle noise using the image restoration process. The restored image is smoothened using Gabor filter and the subsequent image is enhanced by histogram equalization. The preprocessed image is achieved with level set segmentation to detect the stone region. Segmentation process is employed twice for getting better results; first to segment kidney portion and then to segment the stone portion, respectively. In this work, the level set segmentation uses two terms, namely, momentum and resilient propagation (<svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-5.36452pt" id="M1" height="13.8895pt" version="1.1" viewBox="-0.0498162 -8.52498 25.9919 13.8895" width="25.9919pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g190-83" d="M631 18C609 24 585 35 559 65C534 91 514 117 478 169C448 214 406 281 389 313C462 346 516 399 516 485C516 545 490 590 449 616C412 641 363 650 290 650H42V622C120 615 128 612 128 527V125C128 40 120 34 38 28V0H300V28C221 34 212 40 212 125V284H244C295 284 312 272 329 244C359 195 395 133 430 84C475 19 516 -3 592 -7C603 -8 615 -8 627 -8L631 18ZM212 316V563C212 591 215 602 223 607C231 613 248 617 277 617C352 617 423 577 423 469C423 415 407 375 368 345C343 324 310 316 260 316H212Z"/></g><g transform="matrix(.0091,0,0,-0.0091,8.103,3.132)"><path id="g190-113" d="M169 380V459C122 440 66 423 24 416V392C86 384 90 382 90 317V-135C90 -201 81 -207 17 -213V-240H253V-213C176 -207 169 -201 169 -125V6C182 -1 208 -11 238 -12C368 12 487 109 487 260C487 358 421 449 310 449C298 449 279 444 261 433L169 380ZM169 346C196 367 237 389 269 389C341 389 403 329 403 221C403 109 347 37 263 37C228 37 191 53 169 76V346Z"/></g><g transform="matrix(.0091,0,0,-0.0091,12.762,3.132)"><path id="g190-115" d="M181 342V451C133 431 89 419 40 411V388C98 381 102 377 102 311V104C102 38 95 32 33 26V0H263V26C186 32 181 38 181 104V287C203 343 235 372 261 372C277 372 289 366 304 352C310 346 318 345 330 350C349 359 362 379 362 399C362 422 338 449 304 449C256 449 213 393 183 342H181Z"/></g><g transform="matrix(.0091,0,0,-0.0091,16.019,3.132)"><path id="g190-112" d="M257 449C165 449 37 374 37 209C37 98 119 -12 256 -12C355 -12 473 65 473 226C473 349 381 449 257 449ZM244 416C333 416 380 320 380 204C380 67 329 21 267 21C184 21 130 115 130 241C130 354 184 416 244 416Z"/></g><g transform="matrix(.0091,0,0,-0.0091,20.56,3.132)"><use xlink:href="#g190-113"/></g></svg>) to detect the stone portion. After segmentation, the extracted region of the kidney stone is given to Symlets, Biorthogonal (bio3.7, bio3.9, and bio4.4), and Daubechies lifting scheme wavelet subbands to extract energy levels. These energy levels provide evidence about presence of stone, by comparing them with that of the normal energy levels. They are trained by multilayer perceptron (MLP) and back propagation (BP) ANN to classify and its type of stone with an accuracy of 98.8&#x25;. The prosed work is designed and real time is implemented on both Filed Programmable Gate Array Vertex-2Pro FPGA using Xilinx System Generator (XSG) Verilog and Matlab 2012a.

Kalannagari Viswanath

Ramalingam Gunasundari

Analysis and Implementation of Kidney Stone Detection by Reaction Diffusion Level Set Segmentation Using Xilinx System Generator on FPGA

The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware systems more challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying the design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points, and detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation aspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this paper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage model, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted experiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality of the testbench.

Kai Huang

Peng Zhu

Rongjie Yan

Xiaolang Yan

Functional Testbench Qualification by Mutation Analysis

With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

P. K. Biswal

K. Mishra

S. Biswas

H. K. Kapoor

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17&#x25; total average power compared to conventional scan cell that has no gating logic and up to 44.79&#x25; compared to one of the most common existing gating architectures.

Mahshid Mojtabavi Naeini

Chia Yee Ooi

A Novel Scan Architecture for Low Power Scan-Based Testing

A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (&#x3e;20&#x2009;dB) and low noise figure (&#x3C;6&#x2009;dB) provides a wide tuning frequency span (1&#x2013;2.04&#x2009;GHz) to accept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness of the BPF after calibration from process variations, operating in 1.04&#x2009;GHz tuning frequency span: almost zero deviation on center frequency, an average maximum deviation 1.16&#x2009;dB on a nominal pass band gain of 55.6&#x2009;dB, and an average maximum deviation 1.06&#x2009;MHz on a nominal bandwidth of 12.3&#x2009;MHz.

Jian Chen

Chien-In Henry Chen

Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection

Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS)
				 circuits play important roles in both depressing reset noise and conditioning integration signals. 
				  To adapt applications for focal planes of large format and high density, a new structure of CDS
				   circuit occupying small layout area is proposed, whose power dissipation has been optimized by
				    using MOSFETs  in operation of subthreshold region, which leads to 720&#x2009;nW. Then the
				     noise calculation model is established, based on which the noise analysis has been carried out
				      by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. 
				       The results are in good agreement, demonstrating the validity of the present noise calculation model. 
				        Thermal noise plays a dominant role in the long wave situation while <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-3.571899pt" id="M1" height="13.2498pt" version="1.1" viewBox="-0.0498162 -9.6779 20.9604 13.2498" width="20.9604pt"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path id="g113-50" d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z"/></g><g transform="matrix(.0135,0,0,-0.0135,6.503,0)"><path id="g113-48" d="M368 703H309L44 -163H104L368 703Z"/></g><g transform="matrix(.0135,0,0,-0.0135,12.09,0)"><path id="g113-103" d="M619 670C619 686 593 712 555 712S459 686 410 634S335 504 320 430H250L219 400L222 388H312L258 73C223 -133 201 -166 187 -180C175 -191 158 -199 140 -199C123 -199 88 -188 74 -172C68 -166 63 -164 54 -171C38 -185 23 -201 23 -215C23 -236 60 -261 93 -261C122 -261 161 -247 207 -200C268 -138 300 -71 337 94C365 220 376 277 394 387L501 399L521 430H401C432 623 464 665 501 665C524 665 544 651 567 627C577 617 583 618 592 625C601 631 619 651 619 670Z"/></g></svg> noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

A New CDS Structure for High Density FPA with Low Power

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