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Physics Research International
/
2008
/
Article
/
Fig 3
/
Research Letter
Current Tunnelling in MOS Devices with
A
l
2
O
3
/
S
i
O
2
Gate Dielectric
Figure 3
I-V simulations on Al
2
O
3
/SiO
2
and SiO
2
/Al
2
O
3
dielectric stacks for NMOS with the EOT (1 nm). I-V simulation on Al
2
O
3
dielectric is given for comparison.
