Current Tunnelling in MOS Devices with
<svg style="vertical-align:-4.67647pt;width:105.2375px;" id="M1" height="21.262501" version="1.1" viewBox="0 0 105.2375 21.262501" width="105.2375" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(1.25,0,0,-1.25,0,21.2625)"><g transform="translate(72,-54.99)"><text transform="matrix(1,0,0,-1,-71.95,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">A</tspan><tspan style="font-size: 17.93px; " x="12.947626" y="0">l</tspan></text><text transform="matrix(1,0,0,-1,-54.02,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">2</tspan></text><text transform="matrix(1,0,0,-1,-47.24,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">O</tspan></text><text transform="matrix(1,0,0,-1,-34.3,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">3</tspan></text><text transform="matrix(1,0,0,-1,-27.52,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">/</tspan><tspan style="font-size: 17.93px; " x="4.985374" y="0">S</tspan><tspan style="font-size: 17.93px; " x="14.956122" y="0">i</tspan><tspan style="font-size: 17.93px; " x="19.941496" y="0">O</tspan></text><text transform="matrix(1,0,0,-1,5.37,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">2</tspan></text></g></g></svg> Gate Dielectric

<table>I-V simulations on Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> dielectric stacks 
with carrier trap for different trap widths.</table>

Physics Research International

fig4

Figure 4

Figure 4: Current Tunnelling in MOS Devices with
<svg style="vertical-align:-4.67647pt;width:105.2375px;" id="M1" height="21.262501" version="1.1" viewBox="0 0 105.2375 21.262501" width="105.2375" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(1.25,0,0,-1.25,0,21.2625)"><g transform="translate(72,-54.99)"><text transform="matrix(1,0,0,-1,-71.95,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">A</tspan><tspan style="font-size: 17.93px; " x="12.947626" y="0">l</tspan></text><text transform="matrix(1,0,0,-1,-54.02,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">2</tspan></text><text transform="matrix(1,0,0,-1,-47.24,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">O</tspan></text><text transform="matrix(1,0,0,-1,-34.3,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">3</tspan></text><text transform="matrix(1,0,0,-1,-27.52,59.7)"><tspan style="font-size: 17.93px; " x="0" y="0">/</tspan><tspan style="font-size: 17.93px; " x="4.985374" y="0">S</tspan><tspan style="font-size: 17.93px; " x="14.956122" y="0">i</tspan><tspan style="font-size: 17.93px; " x="19.941496" y="0">O</tspan></text><text transform="matrix(1,0,0,-1,5.37,55.22)"><tspan style="font-size: 12.55px; " x="0" y="0">2</tspan></text></g></g></svg> Gate Dielectric 

Physics Research International

Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

Figure 4

Current Tunnelling in MOS Devices with Gate Dielectric