Research Article
Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications
Table 1
Features summarized of flip-flop designs.
| | Pulse-triggered flip-flop Designs | Design [6] | Proposed design |
| | Edge triggering mode | Double | Single | Double | | Number of transistors | 21 | 21 + 2 (Inverter) | | Layout area (um2) | 249.21 | 271.09 | | Setup time (pS) | −216 | −225 | −220 | | Hold time (pS) | 70 | 79 | 73 | | Data-to-Q (pS) | 157 | 157 | 158 | | PDPDQ (fJ) | 20.81 | 21.53 | 19.08 |
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