Research Article
DFAL: Diode-Free Adiabatic Logic Circuits
Table 1
Specifications for simulation.
| Process/MOS model | 0.18 μm CMOS/BSIM3v3.2 | Simulator | VIRTUOSO SPECTRE: CADENCE | MOS dimensions | 0.24/0.18 for all logic circuits* | Clock rate () | Two times the data rate () |
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*All sizes are in m.
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