DFAL: Diode-Free Adiabatic Logic Circuits

<table class="table-group" id="tab1"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">Process/MOS model</td><td align="center">0.18 <i>μ</i>m CMOS/BSIM3v3.2</td></tr><tr><td align="left">Simulator</td><td align="center">VIRTUOSO SPECTRE: CADENCE</td></tr><tr><td align="left">MOS dimensions</td><td align="center">0.24/0.18 for all logic circuits*</td></tr><tr><td align="left">Clock rate (<svg height="20.112499" id="M25" style="vertical-align:-6.33357pt" version="1.1" viewbox="0 0 23.0375 20.112499" width="23.0375" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.162)"><path d="M619 670q0 -13 -9 -26t-18 -19q-13 -10 -25 2q-36 38 -66 38q-31 0 -54.5 -50t-45.5 -185h120l-20 -31l-107 -12q-23 -138 -57 -293q-27 -122 -55 -184.5t-75 -109.5q-60 -61 -114 -61q-25 0 -47.5 15t-22.5 31q0 17 31 44q11 8 20 -1q10 -11 31 -19t35 -8q26 0 47 19
q34 34 71 253l54 315h-90l-3 12l31 30h70q28 138 90 204q35 37 75 57.5t70 20.5q26 0 45 -14t19 -28z" id="x1D453"></path></g>
<g transform="matrix(.012,-0,0,-.012,10.975,17.2)"><path d="M169 380l92 53q26 16 49 16q80 0 128.5 -56t48.5 -133q0 -108 -72.5 -180.5t-176.5 -91.5q-38 1 -69 18v-131q0 -57 13 -70t71 -18v-27h-236v27q49 5 61 17t12 61v452q0 48 -9.5 58.5t-56.5 16.5v24q66 11 145 43v-79zM169 346v-270q37 -39 94 -39q63 0 101.5 50
t38.5 134q0 78 -38.5 123t-95.5 45q-45 0 -100 -43z" id="x70"></path></g><g transform="matrix(.012,-0,0,-.012,17.317,17.2)"><path d="M390 111l17 -21q-34 -45 -80 -73.5t-89 -28.5q-91 0 -146 62t-55 147q0 118 101 195q74 57 149 57h1q59 0 90 -27q16 -14 16 -30q0 -15 -12 -29t-21 -14q-8 0 -19 11q-44 41 -101 41q-52 0 -87.5 -42.5t-35.5 -117.5q0 -49 15 -87t39 -58t49 -30t48 -10q33 0 60.5 12
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</svg>)</td><td align="center">Two times the data rate (<svg height="17.262501" id="M26" style="vertical-align:-4.0404pt" version="1.1" viewbox="0 0 21.362499 17.262501" width="21.362499" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,12.162)"><path d="M619 670q0 -13 -9 -26t-18 -19q-13 -10 -25 2q-36 38 -66 38q-31 0 -54.5 -50t-45.5 -185h120l-20 -31l-107 -12q-23 -138 -57 -293q-27 -122 -55 -184.5t-75 -109.5q-60 -61 -114 -61q-25 0 -47.5 15t-22.5 31q0 17 31 44q11 8 20 -1q10 -11 31 -19t35 -8q26 0 47 19
q34 34 71 253l54 315h-90l-3 12l31 30h70q28 138 90 204q35 37 75 57.5t70 20.5q26 0 45 -14t19 -28z" id="x1D453"></path></g>
<g transform="matrix(.012,-0,0,-.012,10.975,17.2)"><path d="M135 536q-20 0 -35 15.5t-15 35.5q0 22 15 37t36 15t35.5 -15t14.5 -37q0 -21 -15 -36t-36 -15zM252 0h-220v26q48 5 59 17t11 63v206q0 47 -9 58t-54 18v24q78 12 142 39v-345q0 -51 11.5 -63t59.5 -17v-26z" id="x69"></path></g><g transform="matrix(.012,-0,0,-.012,14.164,17.2)"><path d="M524 0h-209v26q44 5 55 18t11 65v167q0 114 -91 114q-50 0 -109 -51v-235q0 -50 10 -61.5t55 -16.5v-26h-217v26q51 5 62 17t11 61v206q0 47 -9.5 58.5t-50.5 19.5v23q82 15 139 40v-79l67 47q47 30 83 30q60 0 94.5 -40t34.5 -112v-193q0 -50 10 -61.5t54 -16.5v-26z
" id="x6E"></path></g>
</svg>)</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr><tr class="table-fn"><td>
                *All sizes are in <svg height="12.175" id="M27" style="vertical-align:-3.56265pt" version="1.1" viewbox="0 0 9.5625 12.175" width="9.5625" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,7.675)"><path d="M538 96q-38 -45 -84 -76.5t-71 -31.5q-44 0 -15 117q12 49 18 89h-2q-99 -128 -163 -178q-36 -28 -70 -28q-26 0 -44 38h-2q-16 -69 -16 -129q0 -43 11 -75.5t24 -42.5l1 -6q-7 -12 -24.5 -23t-37.5 -11q-40 0 -40 76q0 52 35 202l94 407l78 24l5 -5q-32 -122 -72 -310
q-7 -33 0 -55t25 -22q36 0 105.5 75t107.5 145l32 146l75 26h10q-50 -197 -78 -347q-7 -38 6 -38q7 0 31 17t47 39z" id="x1D707"></path></g>
</svg>m.<br/></td></tr></table>

International Scholarly Research Notices

tab1

Table 1

Table 1: DFAL: Diode-Free Adiabatic Logic Circuits 