Architecture Analysis of an FPGA-Based Hopfield Neural Network

Table 1

Parameters obtained from the experiments.

Implementation	(Quantity of neurons and stored patterns)	Maximum frequency (MHz)	Maximum output time after clock (ns)	Number of occupied slices
1	16—2	81.390	4.114	8%
2	17—2	62.530	4.114	17%
3	18—2	56.047	4.114	18%
4	19—2	56.182	4.114	19%
5	20—2	51.635	4.114	20%
6	21—2	51.750	4.114	21%
7	22—3	47.115	4.114	26%
8	23—3	47.124	4.114	32%
9	24—3	43.883	4.114	34%
10	25—3	42.754	4.114	39%
11	26—3	40.069	4.114	41%
12	27—3	40.138	4.114	45%
13	28—3	37.818	4.114	47%
14	29—4	39.200	4.114	18%
15	30—4	36.892	4.114	18%
16	31—4	35.462	4.114	20%
17	32—4	33.553	4.114	18%