Table of Contents
Advances in Electrical Engineering
Volume 2017, Article ID 5640926, 16 pages
Research Article

Novel Basic Block of Multilevel Inverter Using Reduced Number of On-State Switches and Cascaded Circuit Topology

1Department of Electrical Engineering, G. H. Raisoni College of Engineering, CRPF Gate No. 3, Hingna Road, Digdoh Hills, Nagpur, Maharashtra 440016, India
2Department of Electrical Engineering, Shri Ramdeobaba College of Engineering & Management, Ramdeo Tekdi, Gittikhadan, Katol Road, Nagpur 440013, India

Correspondence should be addressed to Sanjay Bodkhe; ude.cenkr@bsehkdob

Received 22 November 2016; Revised 7 March 2017; Accepted 21 March 2017; Published 18 April 2017

Academic Editor: George E. Tsekouras

Copyright © 2017 Aparna Prayag and Sanjay Bodkhe. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper a basic block of novel topology of multilevel inverter is proposed. The proposed approach significantly requires reduced number of dc voltage sources and power switches to attain maximum number of output voltage levels. By connecting basic blocks in series a cascaded multilevel topology is developed. Each block itself is also a multilevel inverter. Analysis of proposed topology is carried out in symmetric as well as asymmetric operating modes. The topology is investigated through computer simulation using MATLAB/Simulink and validated experimentally on prototype in the laboratory.