(a) Slice through silver-encapsulated semiconductor core pillar device, showing details of its structure used in a simulation. The height of the InGaAs core is 300 nm. The light gray region between the InGaAs core and silver is the dielectric. The substrate below the pillar is InP. The height parameter can be varied to modify the of the cavity, allowing more or less light from the cavity mode to leak to the outside of the cavity. (b) Plot of quality factor of cavity () versus length of InP stub under the InGaAs. Values were obtained via FDTD simulations. Shows trade off can be made between and emission efficiency. The particular mode simulated here is the TE01 mode, and due to less interaction with the metal, it has a reasonably large maximum .
