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Advances in Power Electronics
Volume 2011 (2011), Article ID 215376, 6 pages
Flash FPGA-Based Numerical Pulse-Width Modulator
LABCATyP, Department of Electronics, Faculty of Engineering, University of Buenos Aires, Buenos Aires, Argentina
Received 1 November 2010; Accepted 8 February 2011
Academic Editor: Jose Pomilio
Copyright © 2011 Ricardo Arias et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
A pulse-width modulator to drive three-phase AC motors is described. It performs a numerical modulation technique, also known as optimum or calculated modulation, but, in order to reduce hardware resources, a hybrid approach merging that calculated modulation with proportional modulation is proposed. The modulator is tested in a flash-based field programmable gate array (FPGA) implementation.
The pulse-width modulation technique is a well-established method of control in motor drives and power converters. PWM has a lot of variations based upon the load type, the power level, and the semiconductor devices used in the converters [1–3].
Microcontrollers, microprocessors, programmable logic, DSPs (digital signal processors), and FPGAs have evolved to attain the ever complex control strategies required to achieve more performance at a lower cost. Modern microcontrollers with three PWMs included are not uncommon nowadays, and FPGAs with embedded 32-bit processors are a fact.
This scenario has made digital PWM (DPWM) a ubiquitous method of power management, ranging from hundreds of megawatts systems to submilliwatts on-chip voltage regulation modules (VRMs) .
This work presents a PWM modulator suitable for AC motor speed control and uninterruptible power sources (UPSs), but since the first application poses an additional problem, namely, the voltage resolution, it is described for such a load.
In  it is stated the high-frequency PWM generation and resolution trade-off. Two solutions are reported in [6, 7] that increase the effective resolution at expenses of additional subharmonic noise to the PWM spectrum.
It is proposed a different way to enhance the resolution at expenses of noise added in the upper side of the spectrum where filtering is less expensive.
The modulator has been tested using a flash-based field-programmable gate array (FPGA) , and block diagrams of the implementation are given.
2. Optimum Modulation
2.1. Ideal Solution
Aiming to improve the dynamic performance of the closed loop control system, an optimum three-phase pulse-width modulator is implemented in order to reduce the closed loop delay.
Other goals of the modulation technique are to reduce the amplitude of the harmonics close to the fundamental while keeping its implementation simple.
In this “optimum” modulator three independent angles were considered. The half cycle of a waveform of this type of modulation is shown in Figure 1, where is the DC voltage applied to the motor and , and are the three angles that specify a quarter period of the waveform. The waveform is extended to a complete period adding odd and shift symmetries.
The Fourier series of the waveform gives (1) as the expression of the peak-voltage amplitude of the harmonic of order :
The ratio between the peak voltage of the fundamental and the DC voltage is the modulation, that is,
To obtain the values of the three independent angles it is sufficient to fix the value of the peak voltage of the fundamental V1 and to force the next two higher harmonics to become negligible. Assuming symmetrical source and balanced load the third-order harmonics form a homopolar system. Then without neutral wire, this harmonic system is forced null. Moreover, harmonics 5th and 7th are equated to zero. These restrictions are summarized in the following:
For every index modulation value m a set of three angles can be found as long as .
2.2. Discrete Solution
To implement the PWM with a digital system such as an FPGA it is necessary to represent the angles of a particular solution with finite precision. Therefore the interval is partitioned in even segments. As a consequence the approximated values of the angles are not an exact solution of (3), that is, harmonics 5th and 7th are not zero unless is taken large enough, increasing the hardware requirements.
To choose a suitable value for , the total harmonic distortion given by (4) (for pure inductive load) is calculated both for the true values of the angles and for the approximated values for different values of :
Proceeding by this way when equals 20 or more, the distortion values true and discrete differ only slightly. In this sense is taken as a large enough number of segments into which is partitioned.
2.3. Amplitude Voltage Resolution
In applications of AC motor speed control a change in the machine velocity needs a proportional voltage change to keep the magnetic flux of the motor constant to prevent saturation.
It is usual to control the motor speed with a resolution of 5% or even more. Therefore to keep the flux constant, the modulator has to vary the amplitude of the fundamental in the same amount.
Figure 2 depitcs the values of , and for modulation indexes ranging from 0.05 to 1.2, in 5% step increments.
It is clear that the three angles vary almost linearly except in the overmodulation range, and span rad, rad, and rad. Hence to vary the voltage amplitude in 5% steps it is necessary to change the angles at least in rad steps, that is, the interval should be partitioned in steps or more to achieve a 5% of voltage amplitude resolution. This demands much more amount of hardware than the previously determinated in Section 2.2. To avoid such an expensive solution a mixed modulation is proposed in the next section.
3. Optimum and Proportional Modulation
To enhance the resolution, a logical XOR operation between the original modulated signal and a high-frequency variable-duty signal was carried out. This resembles a proportional modulation in a chopper. Figure 3 illustrates this operation, where the optimum modulated signal, , is chopped with a high-frequency signal , while the outcoming, , is shown at the bottom of the figure. Only the first quarter of the waveform is shown.
Modifying the duty of the amplitude of the fundamental component of is modified. This is because the chopping diminishes the local average value, causing a fundamental amplitude reduction.
The coefficients of the Fourier series of the resultant signal are expressed by
To further simplify (5) one additional requirement on the chopper signal is introduced forcing (the period of ) to be an integer multiplier of (period of ). This may be stated as
So (5) can be expressed as
With this symmetry the value of the coefficients may be calculated considering that, in the interval , the signal is the logical difference between and . This condition becomes clear from Figure 3.
Taking into consideration this operation the coefficients of can be expressed with the following equations:
Figure 4 shows the spectral components of both signals with round markers and with square markers. It may be seen that the amplitude of fundamental component of is two times the amplitude of the fundamental component of . Besides this, the operation applied before does not deteriorate the spectral characteristics of the modulated signal, specially in the low frequencies (harmonics close to the fundamental). In this way, the user could achieve the desired value of fundamental component without regenerating the previously eliminated harmonics.
In the figure the components near the 100th component became amplified, because the spectrum was periodized. Therefore, the components of m(θ) can be expressed as a periodization of the components, with each period centered in the integer multipliers of (frequency of ).
As it was mentioned before, modifying the duty cycle of changes the amplitude of the fundamental component. For example, in Figure 3 a duty cycle equal to 25% was adopted yielding a decrement of 50% of the original amplitude.
The duty cycle of has to be less than 0.5 because, for this value, becomes zero and further, for values beyond 0.5, inverts its polarity.
Since the interval is partitioned into 24 slots and the XOR operation is essentially a multiplication of signals, while for a 5% in the amplitude resolution it is necessary 393 segments, segments are required to adjust the duty cycle.
Figure 5 shows simulation results for the degree of variation of the amplitude that can be achieved.
4. Physical Implementation
To prove the concepts of this work the system was implemented on a flash-based FPGA. The overall block diagram of the system is shown in Figure 6.
A microcontroller unit, or MCU, allows to load the proper parameters of the PWM modulator through a serial interface.
The optimum modulator is further detailed in Figure 7 and is loaded by the MCU with the desired -bit modulation pattern into a register with serial input and parallel output. The 24-bit string represents a quarter or period of the full waveform and is loaded into a -bit shift register. The state control block alternatively shifts the pattern to the left and then to the right to complete one half of the waveform. Thereafter the operation is repeated but passing the output through an inverter.
The chopper signal generator block is expanded in Figure 8. It has two 8-bit registers, one for the value of the duty and the other to produce a high-frequency signal. The chopper outputs zeros as long as the 8-bit counter value is lower than the value held in the duty registry, thereafter the chopper outputs ones.
Two other blocks are added to the system in order to produce suitable signals to the drivers of the three-phase bridge that controls the motor: a narrow pulse skipper and a dead-time generator.
The narrow pulse skipper or pulse dropper impedes that very short time pulses reach the semiconductor devices of the bridge since its on-off characteristics made them incapable for following very fast transitions. A scheme of this circuit is shown in Figure 9. These narrow pulses are a direct consequence of the XOR operation and can be noticed in Figure 3.
The dead-time insertion circuit is appended to avoid the simultaneous conduction of both upper and lower devices of the bridge during a commutation. This section of the system is illustrated in Figure 10.
The whole system was simulated and programmed into an FPGA, and their functionalities were verified after the place and route stage.
By comparing the spectrums of both signals one may conclude that the chopped version is most modified on the upper frequency range. By changing the ratio in (6) and adding additional banned harmonics, the unwanted distortion may be moved further to higher frequencies, until the pulse dropper puts a limit to protect power devices from heating by high-frequency switching.
The implementation of an optimum digital modulator was successfully done and the main characteristics obtained are the following.(a)The output filtering operation might be avoided when the PWM output is applied to an AC motor because the modulation technique allows to cancel out some undesired harmonic frequencies while the remaining high frequencies are attenuated by the motor coil inductance. More than three angles can be used to eliminate more unwanted harmonics.(b)The implementation is done in a single chip using only a little fraction of the total cells of the FPGA.(c)The implementation performs a modulation process without requiring much CPU time of a microcontroller, like most of the complex commercial modulators; this is because after calculating the angles, they can be stored in the FPGA to generate the PWM output signals inside.(d)An inexpensive hardware solution is proposed to vary the voltage with high resolution for motor speed control applications or VRMs. This approach involves a chopper operation as described above.
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