Advances in Power Electronics

Advances in Power Electronics / 2011 / Article

Research Article | Open Access

Volume 2011 |Article ID 713250 | https://doi.org/10.1155/2011/713250

J. B. Wang, "Primary Droop Current-Sharing Control of the Parallel DC/DC Converters System considering Output Cable Resistance", Advances in Power Electronics, vol. 2011, Article ID 713250, 13 pages, 2011. https://doi.org/10.1155/2011/713250

Primary Droop Current-Sharing Control of the Parallel DC/DC Converters System considering Output Cable Resistance

Academic Editor: Francesco Profumo
Received07 Dec 2010
Accepted09 Feb 2011
Published05 Apr 2011

Abstract

This paper presents a primary droop current-sharing controller that can integrate into voltage feedback controller and, thus, provides a low-cost and simple solution for parallel DC/DC converters system. From the equivalent small-signal model, a two-port network was adapted to describe the output and control variables for designing voltage and droop current-sharing loops. From the analysis results, the designed primary droop current-sharing controller will not affect the original voltage loop gain profile to let the DC/DC converter preserve desire control performance. After designing a stable DC/DC converter with primary droop current-sharing control, the stability of the interconnected parallel DC/DC converters system was studied. When the cable resistance is reduced, when the cable resistance is reduced, the interconnected system might be unstable. Finally, some simulation and experimental results demonstrated the effectiveness of the proposed controller in a prototype parallel DC/DC converters system.

1. Introduction

In general, the server power system infrastructure consists of frond end AC/DC converters to build up high DC voltage and DC/DC converters to provide power to downstream load. The AC/DC converter uses power factor correction control to let the input line current meet the current harmonic specification; furthermore, the second-stage DC/DC converters and the interconnected cables construct a DC-distributed power system. A DC power system consists of many standard DC/DC converters through interconnected cables or copper buses in series or parallel to obtain desire output voltage, current, and power [1ā€“4]. The structures of the interconnected DC power system have four topologies, that is, input series output series, input series output parallel, input parallel output series, and input parallel output series [2, 4]. The series structure can obtain high output voltage or withstand high input voltage; the kernel of the control strategy is to achieve voltage balance operation among the DC/DC converters. As to the parallel operation, high output current is the major advantage. However, the equal current-sharing control among each of DC/DC converters is the key performance index. In the server power system infrastructure, the parallel DC/DC converters system plays the key role to provide low voltage and high output current capability through the delicate designed interconnected system.

In order to obtain equal current-sharing control in the parallel DC/DC converters system, the current-sharing control should be designed. The most prevailing current-sharing control scheme is the active current-sharing control scheme, especially, the master slave and average current-sharing controls [5ā€“10]. The literature [6, 7] provides the key theoretical study in the master slave and average current-sharing controls. However, the control system analysis of the droop current-sharing control seems to have little study. Most of the investigations focused on the steady-state droop voltage characteristics [11ā€“18]. In addition, the interconnection of the DC/DC converters to form the parallel DC power system requires extra cable wires or copper buses. The study depicted suitable cable resistance can improve the stability of the parallel DC/DC converters system [19]. Furthermore, the common mode stability problem caused by the interconnected and system impedances was found in the paper [7]. The results showed the analysis and design method to obtain a stable interconnected system is to design a stable DC/DC converter and then to analysis the stability of the interconnected subsystem [20]. Finally, if the aforementioned analysis is stable, then the whole DC power system is also stable.

The major purposes of this paper are to design a controller that integrates the voltage and droop current-sharing controllers and to investigate the effects of the output cable resistance to the stability of the interconnected system. Firstly, the small signal model of the buck derived converter was derived in term of the two-port network. From the model reveals the cross-coupling effect was caused from the primary droop current-sharing control path. In order to preserve the voltage loop gain profile, the droop controller was proposed to reduce the parameter uncertainty of the DC/DC converter. After designing a stable DC/DC converter primary with droop current-sharing control, the final interconnected system was analyzed. This system consists of many cable wires to parallel connect the output voltages of the DC/DC converters to the system load. Using the circuit theory to analyze this interconnected system found the cable resistance might affect system stability. Through the investigation of a simple interconnected system, the phase margin will reduce when the cable resistance was reduced. In addition, the Spice-based circuit simulation further confirmed this phenomenon. Finally, the design methods of the droop voltage characteristics and controllers are provided in the appendix. Furthermore, some simulations and experimental results are used to demonstrate the aforementioned findings.

2. Modeling of a Parallel DC/DC Converters System with Primary Droop Current-Sharing Control

Figure 1(a) shows a parallel DC/DC converters system with primary droop current-sharing control which consists of š‘ DC/DC converters, and the symbol š‘– denotes the š‘–th DC/DC converter for š‘–=1 to š‘. The interconnection of the DC/DC converters system to load š‘§šæ is modeled as a resistor š‘Ÿš‘¤š‘– for š‘–=1 to š‘. In addition, the notations š‘‰š‘œš‘– and š‘‰š‘œ denote the output voltage of the š‘–th DC/DC converter and actual load voltage. In order to clarify the voltage and primary droop current-sharing controllers, Figure 1(b) details the actual circuits implementation of the š‘–th DC/DC converter, which is an interleaved dual switch forward converter (IDSFC) with one output inductor. Furthermore, the symbols š‘‰refš‘–, š‘‰š‘–, š‘›, š¼š‘œš‘–, and š¼š‘–š‘– denote reference command setting, input voltage, transformer turn ratio, output current, and primary input current, respectively. The voltage controller integrates šŗš‘1(š‘ ) and šŗš‘2(š‘ ) controllers with the šŗdr(š‘ ) droop controller using a simple analog controller and thus provides a low-cost solution. The meanings of the controllers parameters can be comprehended by their notations. The low-pass filter šŗš‘“(š‘ ) senses the primary input current and generates the designed droop voltage command š‘‰dr with respect to different load currents.

Figure 2(a) shows the equivalent small signal circuits of the š‘–th DC/DC converter, where the nominal duty ratio, equivalent secondary voltage, and equivalent series resistances of output capacitor and inductor are š·, š‘‰š‘”, š‘Ÿš‘, and š‘Ÿšæ, respectively, and š‘‰š‘”=š‘‰š‘–/š‘› [21]. Furthermore, the lower case symbols š‘£š‘–, š‘‘š‘–, š‘£š‘”, š‘–š‘”š‘–, š‘–š‘–š‘–, and š‘–š‘œš‘– denote the small signal variables of the aforementioned uppercase notations. For a š‘ parallel DC/DC converters system, the output current of the š‘–th DC/DC converter š¼š‘œš‘– equals to š¼š‘œ/š‘ in an equal current-sharing operating condition, where š¼š‘œ is the total load current, and, thus, the equivalent load resistance of each DC/DC converter is š‘…š‘›=š‘‰š‘œ/š¼š‘œš‘– for small signal analysis. The small signal model of the converter in Figure 2(b) shows that droop current-sharing control via sensing primary input current contains an extra current source, that is, š¼š‘œš‘–š‘‘š‘–. This current source shows an extra coupling effect between input current š‘–š‘–š‘– and duty ratio š‘‘š‘–. Neglecting the perturbation of the input voltage, the small signal model of the š‘–th DC/DC converter is similar to a two-port network as shown in Figure 2(b) to be ī‚øš‘£š‘œš‘–š‘–š‘–š‘–ī‚¹=ī‚øš»š‘–āˆ’š‘§š‘œš‘–š¹š‘‘š‘–š“š‘–š‘–š‘‘ī‚¹ī‚øš‘–š‘–š‘œš‘–ī‚¹,š»š‘–=š‘£š‘œš‘–š‘‘š‘–||||š‘–š‘œš‘–=0,š‘§š‘œš‘–=š‘£š‘œš‘–š‘–š‘œš‘–||||š‘‘š‘–š¹=0,š‘‘š‘–=š‘–š‘–š‘–š‘‘š‘–||||š‘–š‘œš‘–=0,š“š‘–š‘–=š‘–š‘–š‘–š‘–š‘œš‘–||||š‘‘š‘–=0,(1) where input variables are š‘‘š‘– and š‘–š‘œš‘–, and output variables are denoted as š‘£š‘œš‘– and š‘–š‘–š‘–, respectively. The key transfer functions used for analysis latterly list in the appendix. The detailed design and analysis are introduced as follow.

3. Parallel DC/DC Converters System Analysis and Design

3.1. Voltage and Droop Current-Sharing Loops Design

From Figure 2(b), the š‘–th DC/DC converter includes the voltage feedback, and primary droop current-sharing controllers are shown in Figure 3(a); furthermore, Figure 3(b) is its equivalent control block diagram and suitable for control system analysis via signal flow method. As a result, the total loop gain of the š‘–th DC/DC converter is š‘‡loop=š‘‡š‘£+š‘‡dr,š‘‡(2)š‘£=šŗš‘1šŗš‘2š¾š»š‘–š‘‡,(3)dr=š¾š¹š‘‘š‘–šŗš‘“šŗdršŗš‘1,(4) where š‘‡š‘£ and š‘‡dr denote voltage and droop current-sharing loop gains, respectively. Let the droop current-sharing controller design as šŗdr=š‘˜š‘‘šŗš‘2.(5) The gain constant š‘˜š‘‘ can deduce from Figure 1(b) to be š‘…2/š‘…3. Substituting (5) into (4), the total loop gain can be expressed as š‘‡loop=š‘‡š‘£š‘˜(1+Ī”š‘Š),Ī”š‘Š=š‘‘šŗš‘“š¹š‘‘š‘–š»š‘–.(6) In order to preserve the original voltage loop gain profile and not to be affected by the droop current-sharing loop, the transfer function Ī”š‘Š must meet the following criterion: ā€–Ī”š‘Šā€–āˆžā‰Ŗ1.(7) After manipulating the transfer function Ī”š‘Š, the denominators of the transfer functions š»š‘– and š¹š‘‘š‘– can cancel so the resonant peak of the transfer function Ī”š‘Š will not occur. Furthermore, the droop gain constant š‘˜š‘‘ and transformer turn ratio also contribute to let ā€–Ī”š‘Šā€–āˆž less than 1. Properly design the low-pass filter šŗš‘“ to let Ī”š‘Š be proper, and the effect of the transfer function Ī”š‘Š to voltage loop gain could be small. As a result, the transfer function Ī”š‘Š can be regarded as parameter uncertainty of the plant. To reduce parameter uncertainty of the plant, the simple approach is to increase the gain margin of the DC/DC converter. If the gain margin is greater than 10ā€‰dB, the effect of the parameter variations in modeling error can reduce [6]. The great benefit of using the design droop controller depicted in (5) is that the voltage and droop current-sharing controllers can integrate and implement in a single operational amplifier as shown in Figure 1(b). The voltage controller shown in Figure 1(b) is a simple lead-lag controller šŗš‘(š‘ ) which consists of the controllers šŗš‘1(š‘ ) and šŗš‘2(š‘ ), and can be expressed as šŗš‘(š‘ )=šŗš‘1(š‘ )šŗš‘2=ī€·(š‘ )š‘ /šœ”š‘§1+1ī€øī€·š‘ /šœ”š‘§2ī€ø+1ī€·š‘ /šœ”š‘œ1ī€øī€·š‘ /šœ”š‘1+1ī€øī€·š‘ /šœ”š‘2ī€ø,+1(8) where the poles and zeros of the voltage controller are šœ”š‘œ1, šœ”š‘1, šœ”š‘2, šœ”š‘§1, and šœ”š‘§2, respectively, and might be comprehended from (8). A simple pole placement method suggested in the literature [22], and the desired total loop gain can be approximated as š‘‡loop=š‘‡š‘£1(1+Ī”š‘Š)ā‰ˆī€·š‘ /šœ”š‘œī€øī€·š‘ /šœ”š‘2ī€ø+1,(9) where the pole šœ”š‘œ designs to obtain desired bandwidth and phase margin; furthermore, the šœ”š‘2 filters out the switching noise. The detail parameters of the integrated controller are listed in the appendix.

3.2. Interconnected System Analysis

In general, the stable DC/DC converter can be designed by aforementioned pole placement scheme shown in (8). When a lot of stable DC/DC converters are paralleling operation, the interconnection of the DC/DC converters to actual load forms an interconnected system. In the following analysis, the Thevenin theorem and signal flow method were used. From Figure 3(b), the feedback output impedance of the DC/DC converter is š‘§ofš‘–=š“š‘–š‘–šŗš‘“šŗdršŗš‘1š¾š»š‘–+š‘§š‘œš‘–ī€·1+šŗš‘“šŗdršŗš‘1š¾š¹š‘‘š‘–ī€ø1+š‘‡š‘£+š‘‡drā‰…š‘˜š‘‘šŗš‘“š“š‘–š‘–š‘‡š‘£+š‘§š‘œš‘–š‘‡dr1+š‘‡š‘£+š‘‡dr.(10) Obviously, the feedback output impedance of the DC/DC converter with primary droop current-sharing control is discrepant to original feedback output impedance. In fact, the primary droop current-sharing loop affects the feedback output impedance. Furthermore, the transfer function from reference command setting š‘£refš‘– to output voltage š‘£š‘œš‘– can be deduced as š¹š‘–š‘£(š‘ )=š‘œš‘–š‘£refš‘–=šŗš‘1š¾š»š‘–1+š‘‡loop.(11) Then, the equivalent Thevenin small signal model of the parallel DC/DC converters system is showed in Figure 4. Using node analysis at output node, the relations of the output current š‘–š‘œš‘– to reference command š‘£refš‘– of each DC/DC converter for š‘–=1,ā€¦,š‘ are āŽ”āŽ¢āŽ¢āŽ¢āŽ£š¹1š‘£ref1š¹2š‘£ref2ā‹®š¹š‘š‘£refš‘āŽ¤āŽ„āŽ„āŽ„āŽ¦=āŽ”āŽ¢āŽ¢āŽ¢āŽ£š‘§šæ+š‘Ÿš‘¤1+š‘§of1š‘§šæā‹Æš‘§šæš‘§šæš‘§šæ+š‘Ÿš‘¤2+š‘§of2ā‹Æš‘§šæš‘§ā‹®ā‹®ā‹®šæš‘§šæā‹Æš‘§šæ+š‘Ÿš‘¤š‘+š‘§ofš‘āŽ¤āŽ„āŽ„āŽ„āŽ¦Ć—āŽ”āŽ¢āŽ¢āŽ¢āŽ£š‘–š‘œ1š‘–š‘œ2ā‹®š‘–š‘œš‘āŽ¤āŽ„āŽ„āŽ„āŽ¦.(12) The aforementioned matrix in (12) is nonsingular so its inverse matrix exists. Using matrix inversion formula ((š·āˆ’š¶šø)āˆ’1=š·āˆ’1+š·āˆ’1š¶(š¼āˆ’šøš·āˆ’1š¶)āˆ’1šøš·āˆ’1), the output current š‘–š‘œš‘– is āŽ”āŽ¢āŽ¢āŽ¢āŽ£š‘–š‘œ1š‘–š‘œ2ā‹®š‘–š‘œš‘āŽ¤āŽ„āŽ„āŽ„āŽ¦=āŽ§āŽŖāŽŖāŽŖāŽØāŽŖāŽŖāŽŖāŽ©āŽ”āŽ¢āŽ¢āŽ¢āŽ¢āŽ£š‘§1āˆ’10ā‹Æ00š‘§2āˆ’1ā‹Æ0ā‹®ā‹®ā‹®00ā‹Æš‘§š‘āˆ’1āŽ¤āŽ„āŽ„āŽ„āŽ„āŽ¦āˆ’1Ī”ā„ŽāŽ”āŽ¢āŽ¢āŽ¢āŽ¢āŽ¢āŽ¢āŽ¢āŽ£š‘§šæš‘§21š‘§šæš‘§1š‘§2ā‹Æš‘§šæš‘§1š‘§š‘š‘§šæš‘§1š‘§2š‘§šæš‘§22ā‹Æš‘§šæš‘§2š‘§š‘š‘§ā‹®ā‹®ā‹®šæš‘§1š‘§š‘š‘§šæš‘§2š‘§š‘ā‹Æš‘§šæš‘§2š‘āŽ¤āŽ„āŽ„āŽ„āŽ„āŽ„āŽ„āŽ„āŽ¦āŽ«āŽŖāŽŖāŽŖāŽ¬āŽŖāŽŖāŽŖāŽ­Ć—āŽ”āŽ¢āŽ¢āŽ¢āŽ£š¹1š‘£ref1š¹2š‘£ref2ā‹®š¹š‘š‘£refš‘āŽ¤āŽ„āŽ„āŽ„āŽ¦,(13) where š‘§š‘–=š‘Ÿš‘¤š‘–+š‘§ofš‘–,Ī”ā„Žī“=1+š‘š‘—=1š‘§šæš‘§š‘—.(14) If the parameters of the DC/DC converters are identical and symmetric layout interconnected system is designed, that is, the cable resistance is identical. In this condition, The reference command setting š‘£refš‘– of the š‘–th DC/DC converter is perturbed by Ģ‚š‘£refš‘–, and the resulted output current perturbation Ģ‚š‘–š‘œš‘— for š‘—=1,ā€¦,š‘ is Ģ‚š‘–š‘œš‘—=āŽ§āŽŖāŽØāŽŖāŽ©š‘§+(š‘āˆ’1)š‘§šæš‘§ī€·š‘§+š‘š‘§šæī€øĢ‚š‘£refš‘–āˆ’š‘§,š‘—=š‘–,šæš‘§ī€·š‘§+š‘š‘§šæī€øĢ‚š‘£refš‘–,š‘—ā‰ š‘–,š‘—=1,ā€¦,š‘,(15) where š‘§š‘—=š‘§, š‘—=1,ā€¦,š‘. In general, the transfer function š¹š‘– is stable, and if the zeros of the denominator of (14) locate at on left half plane, then the parallel DC/DC converters system is stable. The aforementioned method can be applied to other DC/DC converters like boost converter for example.

4. Simulation and Experiment

Obviously, from (12) to (15), it is very difficult to find the effect of the output cable resistance to system stability. In order to clarify this, an interconnected system equips with two DC/DC converters is analyzed in detail. From Figure 3, one can construct the control system block diagram of the interconnected system as shown in Figure 5(a). Using (9) to (13), the cross coupling effects of the interconnected system depicts in Figure 5(b). The loop gain of the interconnected system is š‘‡š‘§loop=š‘§ofš‘–š‘¦11+š‘§ofš‘—š‘¦22āˆ’š‘§ofš‘–š‘¦12š‘§ofš‘—š‘¦21+š‘§ofš‘–š‘¦11š‘§ofš‘—š‘¦22,(16) where š‘¦11=š‘§šæ+š‘Ÿš‘¤š‘—Ī”š‘˜,š‘¦22=š‘§šæ+š‘Ÿš‘¤š‘–Ī”š‘˜,š‘¦12=š‘¦21š‘§=āˆ’šæĪ”š‘˜,Ī”š‘˜=š‘§šæš‘Ÿš‘¤š‘–+š‘§šæš‘Ÿš‘¤š‘—+š‘Ÿš‘¤š‘–š‘Ÿš‘¤š‘—.(17) If the parameters of the DC/DC converters are identical and symmetric layout of the interconnected system is designed, (16) can be deuced as š‘‡š‘§loop=š‘§ofī€·š‘§of+2š‘§šæ+2š‘Ÿš‘¤ī€øĪ”š‘˜.(18) Substituting the parameters of the IDSFC into the transfer functions š¹š‘‘š‘– and š“š‘–š‘–, the resulted frequency responses are demonstrated in Figure 6. It shows the magnitude of the transfer function š¹š‘‘š‘– is always above 0ā€‰dB due to the extra current source in the small signal model. In addition, the profile of the transfer function š“š‘–š‘– is similar to the transfer function š»š‘– with lower gain. Figure 7 depicts the voltage, droop current sharing, and total loop gains and the parameter uncertainty Ī”š‘Š. One may find ā€–Ī”š‘Šā€–āˆž is ā€“9.91ā€‰dB at 40.9ā€‰KHz and meets the criterion (7) so the effect of the parameter uncertainty is minimized. Therefore, the profiles of the three loop gains are quite similar with different offset. Using the proposed design droop controller in (5), the total loop gain is not affected by the primary droop current-sharing control significantly. The gain and phase margins of the DC/DC converter can be preserved and gained a stable operation. Figure 8 shows the discrepancy of the open-loop and feedback output impedances. It is interesting to find that the feedback output impedance š‘§ofš‘– is greater than output impedance š‘§š‘œš‘– in low frequency range. However, the feedback output impedance š‘§ofš‘– is rolled off as frequency increased and does not have resonant peak phenomenon. In order to clarify the effects of the output cable resistance to stability, two different cable resistances were simulated in the interconnected system loop gain as shown in Figure 9. When the cable resistance is reduced from 1ā€‰mĪ© to 0.1ā€‰mĪ©, the magnitude of the interconnected system loop gain š‘‡š‘§loop is shifted up and leads to reducing phase margin of the system. From the simulation results, the magnitude and phase were not affected either resistance load or paralleling extra 10000ā€‰Ī¼F capacitance load. In this simulation case, the phase margin is 70Ā° with š‘Ÿš‘¤š‘–=1ā€‰mĪ©, but when the cable resistance was reduced to 0.1ā€‰mĪ©, the phase margin is almost vanishing. In order to further find the effects of the output cable resistance, a Spice-based simulation was carried out via Simetrix/Simplis. Figure 10 shows the output current response of the step referent command disturbance in the 1ā€‰mĪ© and 0.1ā€‰mĪ© cases. Figure 9(a) depicts the output currents can subside back into equal current-sharing control in 1ā€‰mĪ© cable resistance case; unfortunately, Figure 10(b) shows the unstable operation via 0.1ā€‰mĪ© cable resistance. This conforms the previous comments that a large cable resistance can improve the system stability [19].

After the simulations have demonstrated the performance of the proposed integrated controller for voltage and droop current-sharing control, the paralleled DC/DC converter system with š‘=2 was implemented. Furthermore, The PWM IC UC3525 was used to generate two-phase PWM pulses to control IDSFC as shown in Figure 1(b). Figure 11(a) shows the measured primary currents and MOSFET drain to source voltage waveforms for referent. It shows the primary currents of the two forward converters are in balance operation. Owing to one output inductor scheme, two power trains of the IDFSC have the same primary side current, which reflects from the secondary side inductor current as shown in Figure 11(b). Furthermore, the hot swap operation is also depicted in Figure 11(c), the parallel IDFSCs can achieve equal sharing control. Figure 12 shows the loop gain profiles of the IDFSC, which are similar to the simulation results. It shows the designed IDFSC has at least 45Ā° phase margin, 10ā€‰dB gain margin, and 10ā€‰KHz bandwidth; therefore, the effects of the parameter uncertainty can reduce significantly. Because the cable length of the prototype IDFSC is 30ā€‰cm with 2ā€‰mĪ© resistance as shown in Figure 13(a), the resulted interconnection system is stable. The physical size of the IDFSC and interconnected system can let the cable length be shorted to 15ā€‰cm, and the resulted cable resistance is 1ā€‰mĪ© as depicted in Figure 13(b). However, it is very difficult to obtain 0.1ā€‰mĪ© cable resistance in this laboratory prototype interconnected system to demonstrate the unstable operation. Fortunately, from the theory study and simulation verification, the cable resistance will affect system stability.

5. Conclusions

An interconnected DC power system consists of DC/DC converters with primary droop current-sharing control was presented in this paper. Using the proposed droop controller will not affect the original design voltage loop gain profile but also can integrate into voltage controller and thus provides a low-cost solution. Furthermore, after a stable DC/DC converter design was achieved, the effect of the cable wire resistances of the interconnected system to stability was also investigated. The results demonstrated that the reduction of the cable resistance will decrease the phase margin of the interconnected system and lead to instability. Properly increasing the cable resistance can improve system stability, but the operating efficiency will reduce. This paper provides a method to evaluate the stability of the interconnected system. Using this method, the engineer can make a tradeoff between system stability and efficiency.


š‘… 1 š‘… 2 š‘… 3 š‘… 4 š‘… 5 š‘… 6 š¶ 1 š¶ 2 š¶ 3 š¶ 4

2.57ā€‰kĪ©10ā€‰kĪ©100ā€‰kĪ©1ā€‰kĪ©33ā€‰kĪ©10ā€‰kĪ©4700ā€‰pF6800ā€‰pF680ā€‰pF220ā€‰pFx2


š‘… š‘“ 1 š‘… š‘“ 2 š¶ š‘“ 1 š¶ š‘“ 2 š‘˜ š‘“

1ā€‰kĪ©100ā€‰Ī©0.1ā€‰Ī¼F0.01ā€‰Ī¼F2.4

Appendix

(1) The Designed Parameters of the Interleaved Dual-Switch Forward Converter Are as Follows.
(i)Primary side DC bus voltage š‘‰š‘–=385ā€‰V.(ii)Primary switching frequency š‘“š‘ =125ā€‰kHz.(iii)Nominal output voltage š‘‰š‘œ=12ā€‰V.(iv)Nominal output current š¼š‘œ=66ā€‰A.(v)Transformer PQ32/30 š‘š‘ƒ=20 turns, š‘š‘ =1 turn, and š‘›=20.(vi)Output inductor MS10675 with inductance šæ=2ā€‰Ī¼H.(vii)Output capacitance š¶=5400ā€‰Ī¼F and esr=4ā€‰mĪ©.(viii)Nominal duty ratio š·=0.62 in the secondary side of the IDSFC with an output inductor.(ix)The gain of the PWM comparator š¾=0.25.

(2) The Key Transfer Functions of the IDFSC
š‘£š‘œš‘–š‘‘š‘–=š»š‘–š‘‰(š‘ )=š‘”š‘…š‘›ī€·š‘ š¶š‘Ÿš‘ī€ø+1Ī”,š‘–š‘–š‘–š‘‘š‘–=š¹š‘‘š‘–š¼(š‘ )=š‘œš‘–+ī€·š·š‘‰š‘”ī€·ī€·š‘…š‘†š¶š‘›+š‘Ÿš‘ī€øī€øī€ø+1/Ī”š‘›,š‘–šæš‘–š‘‘š‘–=š¹š‘‘š‘–šæš‘–š‘‰(š‘ )=š‘”ī€·ī€·š‘†š¶š‘…+š‘Ÿš‘ī€øī€ø+1Ī”,š‘–š‘œš‘–š‘‘š‘–=š¹š‘‘š‘–š‘œš‘–š‘‰(š‘ )=š‘”ī€·š‘†š¶š‘Ÿš‘ī€ø+1Ī”,š‘§š‘œš‘–=š‘£š‘œš‘–š‘–š‘œš‘–=š‘…š‘›ī€·š‘ š¶š‘Ÿš‘+1ī€øī€·š‘ šæ+š‘Ÿšæī€øĪ”,š“š‘–š‘–=š‘–š‘–š‘–š‘–š‘œš‘–=š·š‘…š‘›ī€·š‘ š¶š‘Ÿš‘ī€ø+1Ī”,(A.1) where Ī”=š‘ 2ī€·š‘…šæš¶š‘›+š‘Ÿš‘ī€øī€·ī€·š‘…+š‘ šæ+š¶š‘›š‘Ÿšæ+š‘…š‘›š‘Ÿš‘+š‘Ÿšæš‘Ÿš‘ī€øī€ø+š‘…š‘›+š‘Ÿšæā‰…ī€·š‘…š‘›+š‘Ÿšæī€øīƒ©ī‚µš‘ šœ”š‘›ī‚¶2š‘ +2šœ‰šœ”š‘›īƒŖ+1,š‘…š‘›ā‰«š‘Ÿšæ,š‘Ÿš‘,šœ”š‘›=1āˆš,ī€·š‘…šæš¶šœ‰=š‘+š‘›š‘Ÿšæ+š‘…š‘›š‘Ÿš‘+š‘Ÿšæš‘Ÿš‘ī€ø/š‘2ī€·š‘…š‘›+š‘Ÿšæī€ø,ī‚™š‘=šæš¶.(A.2)

(3) Design Procedure of the Steady-State Output Voltage Droop Characteristic
In general, the output voltage droop characteristic of a DC/DC converter depends on output voltage regulation specification with a predetermined design margin. If the maximum, nominal, and minimum output voltages of the regulation range are denoted as š‘‰š‘œš‘–,max, š‘‰āˆ—š‘œš‘–, and š‘‰š‘œš‘–,min, respectively. From Figure 1(b), the output voltage variation of the š‘–th DC/DC converter with respect to droop current-sharing control is š‘‰š‘œš‘–,max=š‘‰āˆ—š‘œš‘–+Ī”š‘‰š‘œš‘–=š‘‰refš‘–š¾š‘‘,š¼š‘œš‘–=0,(A.3) where š‘‰š‘œš‘–,min=š‘‰āˆ—š‘œš‘–āˆ’Ī”š‘‰š‘œš‘–=š‘‰refš‘–š¾š‘‘āˆ’š‘‰drš¾š‘š‘ š¾š‘‘,(A.4)š¾š‘‘=š‘…1š‘…3š‘…1š‘…2+š‘…1š‘…3+š‘…2š‘…3,š¾š‘š‘ =š‘…1š‘…2š‘…1š‘…2+š‘…1š‘…3+š‘…2š‘…3.(A.5) Furthermore, the droop voltage š‘‰dr synthesizes from primary current through a low-pass filter, which is proportion to output current, that is, š¼š‘–š‘–=š·š¼š‘œš‘–/š‘›. From (A.3) and (A.4), the output voltage deviation Ī”š‘‰š‘œš‘– can be expressed in terms of droop voltage as Ī”š‘‰š‘œš‘–=š‘‰drš¾š‘š‘ 2š¾š‘‘=š‘˜š‘‘š‘‰dr2.(A.6) For a given output voltage deviation Ī”š‘‰š‘œš‘–, the design procedure of the output voltage droop characteristics is suggested as follows.(i)Let š‘…ī…ž1=š‘˜š‘‰refš‘– and š‘˜>0.(ii)The resistance š‘…2 can subsequently be determined from the maximum output voltage listed in (A.3), š¾š‘‘, and š‘…ī…ž1.(iii)For a given specification of the output voltage deviation and droop voltage, the resistances š‘…1 and š‘…3 can be found from (A.6) and resistance š‘…ī…ž1.

(4) Voltage and Primary Droop Current-Sharing Controller
The feedback controllers in Figure 1(b) are šŗš‘1ī€·(š‘ )=š‘ /šœ”š‘§1ī€ø+1š›¼2š‘ ī€·š‘ /šœ”š‘1ī€ø+1,šŗš‘2ī€·(š‘ )=š‘ /šœ”š‘§2ī€ø+1š¾2ī€·š‘ /šœ”š‘2ī€ø+1,(A.7) where šœ”š‘1=1š¶23š‘…5,šœ”š‘2=1š¶1š‘…4,šœ”š‘§1=1š¶2š‘…5,šœ”š‘§2=1š¶1ī€·š‘…2+š‘…4ī€ø,š›¼2=š¶2+š¶3,š¶23=š¶2š¶3š¶2+š¶3,š¾2=š‘…2,šœ”š‘œ1=1š¾2š›¼2.(A.8)(i)The design poles and zeros of the controller šŗš‘1(š‘ ), šŗš‘2(š‘ ), and šŗdr(š‘ ) can let the DC/DC converter have at least 45Ā° phase margin, 10ā€‰dB gain margin, and 10ā€‰KHz bandwidth šœ”0=66845rad/sec,šœ”š‘1šœ”=49019.6rad/sec,š‘2=212765.95rad/sec,šœ”š‘§1šœ”=4456.33rad/sec,š‘§2=20263.24rad/sec.(A.9)(ii)Circuit parameters of the controller šŗš‘1(š‘ ), šŗš‘2(š‘ ), and šŗdr(š‘ ); (see Table 1).

Note
(1) Using the nearest commercial parts instead of the estimated parameters.

(5) Low-Pass Filter šŗš‘“(š‘ )
šŗš‘“=š‘˜(š‘ )š‘“š‘ 2š‘…š‘“1š‘…š‘“2š¶š‘“1š¶š‘“2ī€·š‘…+š‘ š‘“1ī€·š¶š‘“1+š¶š‘“2ī€ø+š‘…š‘“2š¶š‘“2ī€ø.+1(A.10) (see Table 2).

Acknowledgment

The authors thank the National Science Council of Taiwan for supporting the research project: NSC99-2221-E231-036.

References

  1. V. Vorpérian, ā€œSynthesis of medium voltage dc-to-dc converters from low-voltage, high-frequency PWM switching converters,ā€ IEEE Transactions on Power Electronics, vol. 22, no. 5, pp. 1619ā€“1635, 2007. View at: Publisher Site | Google Scholar
  2. R. Ayyanar, R. Giri, and N. Mohan, ā€œActive input-voltage and load-current sharing in input-series and output-parallel connected modular dc-dc converters using dynamic input-voltage reference scheme,ā€ IEEE Transactions on Power Electronics, vol. 19, no. 6, pp. 1462ā€“1473, 2004. View at: Publisher Site | Google Scholar
  3. R. Giri, V. Choudhary, R. Ayyanar, and N. Mohan, ā€œCommon-duty-ratio control of input-series connected modular DC-DC converters with active input voltage and load-current sharing,ā€ IEEE Transactions on Industry Applications, vol. 42, no. 4, pp. 1101ā€“1111, 2006. View at: Publisher Site | Google Scholar
  4. W. U. Chen, X. Ruan, H. Yan, and C. K. Tse, ā€œDC/DC conversion systems consisting of multiple converter modules: stability, control, and experimental verifications,ā€ IEEE Transactions on Power Electronics, vol. 24, no. 6, pp. 1463ā€“1474, 2009. View at: Publisher Site | Google Scholar
  5. S. Luo, Z. Ye, R. L. Lin, and F. C. Lee, ā€œClassification and evaluation of paralleling methods for power supply modules,ā€ in Proceedings of the 30th Annual IEEE Power Electronics Specialists Conference (PESC '99), vol. 2, pp. 901ā€“908, July 1999. View at: Google Scholar
  6. D. S. Garabandic and T. B. Petrovic, ā€œModeling parallel operating PWM DC/DC power supplies,ā€ IEEE Transactions on Industrial Electronics, vol. 42, no. 5, pp. 545ā€“551, 1995. View at: Publisher Site | Google Scholar
  7. V. J. Thottuvelil and G. C. Verghese, ā€œAnalysis and control design of paralleled DC/DC converters with current sharing,ā€ IEEE Transactions on Power Electronics, vol. 13, no. 4, pp. 635ā€“644, 1998. View at: Google Scholar
  8. J. Rajagopalan, K. Xing, Y. Guo, F. C. Lee, and Manners, ā€œModeling and dynamic analysis of paralleled dc/dc converters with master-slave current sharing control,ā€ in Proceedings of the 11th IEEE Applied Power Electronics Conference and Exposition (APEC '96), vol. 2, pp. 678ā€“684, 1996. View at: Google Scholar
  9. Y. Panov, J. Rajagopalan, and F. C. Lee, ā€œAnalysis and design of N paralleled DC-DC converters with master-slave current-sharing control,ā€ in Proceedings of the 12th IEEE Applied Power Electronics Conference and Exposition (APEC '97), vol. 1, pp. 436ā€“442, 1997. View at: Google Scholar
  10. Y. Huang and C. K. Tse, ā€œCircuit theoretic classification of parallel connected dc-dc converters,ā€ IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 5, pp. 1099ā€“1108, 2007. View at: Publisher Site | Google Scholar
  11. Y. Panov and M. M. Jovanović, ā€œLoop gain measurement of paralleled dc-dc converters with average-current-sharing control,ā€ in Proceedings of the 23rd Annual IEEE Applied Power Electronics Conference and Exposition (APEC '08), pp. 1048ā€“1053, February 2008. View at: Publisher Site | Google Scholar
  12. I. Batarseh, K. Siri, and H. Lee, ā€œInvestigation of the output droop characteristics of parallel-connected DC-DC converters,ā€ in Proceedings of the 25th Annual IEEE Power Electronics Specialists Conference (PESC '94), vol. 2, pp. 1342ā€“1351, June 1994. View at: Google Scholar
  13. J. Perkinson, ā€œCurrent sharing of redundant DC-DC converters in high availability systems—a simple approach,ā€ in Proceedings of the IEEE 10th Annual Applied Power Electronics Conference (APEC '95), vol. 2, pp. 952ā€“956, March 1995. View at: Google Scholar
  14. Brian T. Irving and Milan M. Jovanovic, ā€œAnalysis, design, and performance evaluation of droop current-sharing method,ā€ in Proceedings of the IEEE Applied Power Electronics Conference and Exposition (APEC '00), vol. 1, pp. 235ā€“241, 2000. View at: Google Scholar
  15. J. W. Kim, H. S. Choi, and B. O. H. Cho, ā€œA novel droop method for converter parallel operation,ā€ IEEE Transactions on Power Electronics, vol. 17, no. 1, pp. 25ā€“32, 2002. View at: Publisher Site | Google Scholar
  16. X. Zhou, P. Xu, and F. C. Lee, ā€œA novel current-sharing control technique for low-voltage high-current voltage regulator module applications,ā€ IEEE Transactions on Power Electronics, vol. 15, no. 6, pp. 1153ā€“1162, 2000. View at: Google Scholar
  17. J. A. Abu Qahouq, L. Huang, and D. Huard, ā€œSensorless current sharing analysis and scheme for multiphase converters,ā€ in Proceedings of the IEEE 38th Annual Power Electronics Specialists Conference (PESC '07), pp. 2029ā€“2036, June 2007. View at: Publisher Site | Google Scholar
  18. H. Mao, L. Yao, C. Wang, and I. Batarseh, ā€œAnalysis of inductor current sharing in nonisolated and isolated multiphase DC-DC converters,ā€ IEEE Transactions on Industrial Electronics, vol. 54, no. 6, pp. 3379ā€“3388, 2007. View at: Google Scholar
  19. T. F. Wu, K. Siri, and J. Banda, ā€œCentral-limit control and impact of cable resistance in current distribution for parallel-connected DC-DC converters,ā€ in Proceedings of the 25th Annual IEEE Power Electronics Specialists Conference (PESC '94), vol. 1, pp. 694ā€“702, June 1994. View at: Google Scholar
  20. J. Lunze, Feedback Control of Large-Scale Systems, Prentice Hall, New York, NY, USA, 1992.
  21. R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, Kluwer Academic, Boston, Mass, USA, 2nd edition, 2001.
  22. M. Brown, Power Supply Cookbook, Butterworth-Heineman, Oxford, UK, 1994.

Copyright © 2011 J. B. Wang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


More related articles

 PDF Download Citation Citation
 Download other formatsMore
 Order printed copiesOrder
Views3335
Downloads1574
Citations

Related articles

We are committed to sharing findings related to COVID-19 as quickly as possible. We will be providing unlimited waivers of publication charges for accepted research articles as well as case reports and case series related to COVID-19. Review articles are excluded from this waiver policy. Sign up here as a reviewer to help fast-track new submissions.