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Chinese Journal of Engineering
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Chinese Journal of Engineering
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2013
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Article
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Fig 8
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Research Article
Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA
Figure 8
(a) System generator Syn_lock, (b) System generator Received bits, (c) Transmitted bits, (d) Hardware cosim Received bits, and (e) Hardware cosim Sync_lock.
(a)
(b)
(c)
(d)
(e)