Area Efficient Implementation of MTI Processing Module on a Reconfigurable Platform

Table 2

Implementation results.

Implementation	Device	Clock rate; (MHz)	FPGA area; (slices)	Throughput/slice; (TPA)
Our design 1	Xc3s500e	144.8	1336	0.108
Our design 2	Xc3s500e	122.639	107	1.146
Other work [3]	Virtex-4 SX35	183.55	1075	0.170
Other work [3]	Virtex-4 SX35	177.70	1382	0.128
Other work [11]	Virtex-II Pro (ML-300)	0.11	1468	—
Other work [9]	XC2V6000	102.17	811	—

Bold values emphasize superiority of results.