Research Article  Open Access
Bahram Dehghan, "Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate", Chinese Journal of Engineering, vol. 2014, Article ID 532121, 7 pages, 2014. https://doi.org/10.1155/2014/532121
Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate
Abstract
Quantumdot cellular automata (QCA) suggest an emerging computing paradigm for nanotechnology. The QCA offers novel approach in electronics for information processing and communication. QCA have recently become the focus of interest in the field of low power nanocomputing and nanotechnology. The fundamental logic elements of this technology are the majority voter (MV) and the inverter (INV). This paper presents a novel design with less garbage output and minimum quantum cost in nanotechnology. In the paper we show how to create multipurpose reversible gates. By development of suitable gates in logic circuits as an example, we can combine MFA and HS in one design using CMVMIN gate. We offer CMVMIN gate implementations to be used in multipurpose circuit. We can produce concurrent half adder/subtractor and one bit comparator in one design using reversible logic gates and CMVMIN gates. Also, a decoder from recent architecture has been shown independently. We investigate the result of the proposed design using truth table. A significant improvement in quality of the calculated parameters and variety of required outputs has been achieved.
1. Introduction
This heat dissipation extremely reduces the performance and lifetime of the circuits. The solution is to use revolutionary technology which enables extremely low power consumption and heat waste in computing [1]. Reversible logic gates are extensively known to be compatible with future computing technologies which approximately dissipate zero heat [2]. Reversible are the circuits or the gates that have the same number of inputs and outputs and have onetoone mappings between vectors of inputs and outputs; thus, the vector of the input states can be uniquely reconstructed from the vector of the output states [3].
The QCA (Quantumdot cellular automata) are considered to be the promising technology for future generation ICs that overcome the limitations of CMOS. The fundamental unit of QCA based design is the 3input majority gate (majority voter, MV) and the inverter. The wide acceptance of QCA in logic design attracts researchers to explore new universal gate structures targeting cost effective realization [4]. Existing synthesis tools do not make efficient use of MV in technology mapping for synthesis of logic designs. Even for arithmetic circuits, in which there should be perfect matches for the MV, the synthesis tools rarely find any matches [5].
This satisfies the requirement of optimum logic gates as well as minimum number of garbage outputs in an energy efficient design [6]. We illustrate CMVMIN gate with the target to reduce the number of logic gates and garbage outputs. In this work, we propose the use of CMVMIN gate as a basic of multipurpose circuit. We can construct other multipurpose circuits similarly.
2. Fundamental Reversible Gates
Because of their easiness and quantum realization cost there are design approaches and tools that incorporate them separately or in combination with each other. The quantum cost of a reversible circuit is the number of primary quantum gates required to implement a circuit [7]. Any reversible gate performs the permutation of its input patterns only and realizes the functions that are reversible. If a reversible gate has inputs, and therefore outputs, then we call it a reversible gate [8]. We demonstrate the application of the reversible gate to design multipurpose circuit. Firstly, in order to derive the results we review the characterization of FG and PG gates. In Feynman gate, one of the input bits act as control signal (). That is, if then the output follows the input . If then the input is flipped at the output . Because of this, it is called controlled NOT (1NOT) and also called quantum XOR because of its popularity in the field of quantum computing [9]. Feynman gate (CNOT gate) is shown in Figure 1.
A one through reversible gate called Peres gate (PG) is introduced. Figure 2 shows the Peres gate as the reversible gate.
Also, the block diagram of RUG is shown in Figure 3. Since use of this universal function helps the realization of XNOR/XOR easily, the RUG can enable low cost realization of many other complex Boolean functions [6]. Another reversible gate, namely, IG gate, is presented in Figure 4 [8]. The application of these gates is described in the following sections.
3. The QCA Basics
The QCA (Quantumdot cellular automata) are considered to be a promising technology to meet such a design target [6]. QCA have significant advantages in terms of power dissipation as they do not have to dissipate all their signal energy, hence, considered one of the promising technologies to achieve the thermodynamic limit of computation [10]. A QCA cell consists of two electrons positioned at opposite corners owing to coulombic repulsion, so the polarization states of and can be represented by two stable configurations of a pair of electrons; the corresponding logic values of “0” and “1” also are represented in Figure 5. A majority gate with the logic function of MV is composed of five cells. By setting one of the inputs of this gate permanently to 0 or 1, AND and OR functions will be formed in QCA [11]. We review NNI gate as the basic logic element for QCA based designs. This 3input gate realizes the function .
A QCA circuit can be efficiently built using majority gates and inverters. QCA majority gate is shown in Figure 6.
4. Coupled MajorityMinority Gate
In QCA, coplanar wire crossings are one of the very elegant features of this new low power computing paradigm. However, these need two types of cells and are known to be neither easy to fabricate nor very robust. In QCA based logic design, the utmost necessity is to ensure least number of wire crossings due to its single layer restriction [11].
The coupled majorityminority (CMVMIN) QCA gate structure simultaneously realizes 3input minority logic (MIN) and majority voter (MV) in its 2 outputs and (Figure 7). The is the complement of . This gate is also realizable with a tile structure. The truth table of CMVMIN gate is shown in Table 1. This gate can function as an ANDNAND gate ( and ) when input is set to logic 0. Similarly, it can simultaneously realize OR and NOR functions when is set to 1.

(a) Gate structure 1
(b) Gate structure 2
(c) Symbol
Two structures are shown in Figures 7(a) and 7(b). The symbol of this gate is illustrated in Figure 7(c) [12].
5. Design Multipurpose Circuit
The major consideration in implementing the proposed multipurpose circuit is to enhance its speed as much as possible [13]. We could achieve some other various states configurations of logic circuits in quantum information and quantum computation [14].
Firstly, the design capability of RUG will be evaluated in implementing multipurpose circuits. If , then the outputs will be achieved according to Figure 8. One and three outputs represent the carry and sum of a half adder, respectively. Results of RUG are shown in Figure 8.
Now, we propose half adder/subtractor architecture in one design using RUG and two Feynman gates. The design of a mentioned circuit is presented which is implemented with minimum gates and garbage outputs. Results are shown in Figure 9. Table 2 shows the evaluation of the mentioned circuit.

On the other hand, we can demonstrate our goal with IG gate that its obtained result has better performance than previous structure. If inputs and are equal to zero, then the circuit will be depicted as follows. Hence, the mentioned circuit requires one reversible gate (IG gate) and produces one garbage output. The architecture of this gate is demonstrated in Figure 10. Table 3 shows the evaluation of the mentioned circuit.

Now, let us consider a function of conventional gates investigated by truth table. We realized the EXOR and EXNOR gates with the following equations. Table 4 shows the operation of the logic circuit topics. We have A symmetric function means a Boolean function invariant to the permutation of any of its input variables [3]. Figure 11 points to the fact that only three CMVMIN gates are needed to realize all such 6 symmetric functions.

According to Table 4, by combining CMVMIN gate and Feynman gate, we can generate EXOR and EXNOR gates. Figures 12 and 13 show a combination of CMVMIN gates and FG gates.
Adder is profoundly used in the generic computer because it is very noticeable for adding data in the processor. The MCLA [15] uses the modified full adder (MFA) as shown in Figure 14. The major consideration in implementing the proposed multipurpose circuit is to enhance its speed as much as possible. On the other hand, the equations of borrow and difference for half subtractor are as follows: Figure 15 is obtained by combining the two mentioned circuits. Table 5 shows the evaluation of the proposed design.

We can produce half subtractor, half adder, and one bit comparator in one design using Peres gate and CMVMIN gates. The proposed circuit of Figure 16 is evaluated in terms of number of reversible gates used and garbage outputs produced.
Table 6 shows the evaluation of the proposed design.

The following circuit has another application that is as a 2 × 4 decoder. Decoder is significant component and it is utilized in many logical and functional circuits. A decoder is a multipleinput, multipleoutput logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. Figure 17 shows a 2 × 4 decoder. The behaviour of mentioned conventional circuit is defined as follows:
Hence, another proposed circuit implementation using additional Feynman gate is presented in Figure 18.
Figure 18 has been utilized to implement new aspect from available circuit. Table 7 shows the evaluation of the proposed design.

We see that the mentioned circuit performs significantly appropriate in terms of the number of gates and the number of garbage outputs. As we have seen, this multipurpose circuit produces only one garbage output. Therefore, we can infer that the proposed structure will successfully implement mentioned multipurpose circuit.
6. Conclusion
Reversible logic has had promising interest in the recent past due to its less heat dissipating characteristics. An important purpose in our designs was to ensure that the designs are practical and usable. We present a novel design for concurrent half adder/subtractor scheme using RUG and two Feynman gates. However, these fundamental results motivate realizations of the same circuit using IG gate with better performance. One aim of this paper is to evaluate the CMVMIN gate in the available logic circuits with capable versatility and minimum garbage outputs susceptibility. Also, results are verified by the truth table. In addition, the last design is proposed for the multipurpose circuits in terms of garbage output and gate count that was not ever seen. It clearly shows the capabilities and characteristics of CMVMIN gate for designing circuits. Also, we can generalize this concept to the other families of reversible gates. The experimental results illustrate that reversible logic is less likely to exhibit redundant logic than irreversible logic.
Conflict of Interests
The author declares that there is no conflict of interests regarding the publication of this paper.
References
 B. Dehghan, “Design of asynchronous sequential circuits using reversible logic gates,” , International Journal of Engineering and Technology, vol. 4, no. 4, pp. 213–219, 2012. View at: Publisher Site  Google Scholar
 B. Dehghan, “Survey the inverse property of quantum gates for concurrent error detection,” Journal of Basic and Applied Scientific Research, vol. 3, no. 2, pp. 603–608, 2013. View at: Google Scholar
 P. K. Bhattacharjee, “Use of symmetric functions designed by QCA gates for next generation IC,” International Journal of Computer Theory and Engineering, vol. 2, no. 2, pp. 211–217, 2010. View at: Google Scholar
 M. Dalui, B. Sen, and B. K. Sikdar, “Fault tolerant QCA logic design with coupled majorityminority gate,” International Journal of Computer Applications, vol. 1, no. 29, pp. 81–87, 2010. View at: Publisher Site  Google Scholar
 M. Momenzadeh, J. Huang, M. B. Tahoori, and F. Lombardi, “Characterization, test, and logic synthesis of andorinverter (AOI) gate design for QCA implementation,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 24, no. 12, pp. 1881–1892, 2005. View at: Publisher Site  Google Scholar
 B. Sen, T. Adak, A. S. Anand, and B. K. Sikdar, “Synthesis of reversible universal QCA gate structure for energy efficient digital design,” in Proceedings of the IEEE Region 10 Conference: Trends and Development in Converging Technology Towards 2020, pp. 806–810, November 2011. View at: Publisher Site  Google Scholar
 B. Dehghan, “Generating new reversible logic gates with ladder block structure for emerging nanocircuits,” Journal of Basic and Applied Scientific Research, vol. 3, no. 1, pp. 610–615, 2013. View at: Google Scholar
 M. S. Islam, M. M. Rahman, Z. Begum, M. Z. Hafiz, and A. Al Mahmud, “Synthesis of fault tolerant reversible logic circuits,” in Proceedings of the IEEE International Conference on Circuits and Systems, April 2009, http://arxiv.org/ftp/arxiv/papers/1008/1008.3340.pdf. View at: Publisher Site  Google Scholar
 X. S. Christina and M. S. Justine, “Realization of BCD adder using reversible logic,” International Journal of Computer Theory and Engineering, vol. 2, no. 3, pp. 333–337, 2010. View at: Google Scholar
 H. Thapliyal and N. Ranganathan, “Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits,” in Proceedings of the 22nd International Conference on VLSI Design, pp. 511–516, January 2009. View at: Publisher Site  Google Scholar
 R. Zhou, X. Xia, F. Wang, Y. Shi, and H. Liaoa, “Logic circuit design of 24 decoder using quantum cellular automata,” Journal of Computational Information Systems, vol. 8, no. 8, pp. 3463–3469, 2012. View at: Google Scholar
 S. Ditti, K. Mahata, P. Mitra, and B. K. Sikdar, “Defect characterization in coupled majorityminority QCA gate,” in Proceedings of the 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, pp. 293–298, IEEE, April 2009. View at: Publisher Site  Google Scholar
 B. Dehghan, “Characterization and logic synthesis of URG gate for designing multipurpose circuits,” European Journal of Scientific Research, vol. 105, no. 1, pp. 117–125, 2013. View at: Google Scholar
 B. Dehghan and A. A. Baziar, “Optimized methodology for realization of logic circuits using QCA gates,” International Journal of Advanced Research in Computer Science and Software Engineering, vol. 3, no. 3, pp. 58–61, 2013. View at: Google Scholar
 Y.T. Pai and Y.K. Chen, “The fastest carry lookahead adder,” in Proceedings of the 2nd IEEE International Workshop on Electronic Design, Test and Applications, pp. 434–436, January 2004. View at: Google Scholar
Copyright
Copyright © 2014 Bahram Dehghan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.