DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Table 3

Experimental parameters and meanings.

Parameter	Value	Meaning
	0.33	Probability that the triggered HT in the chiplet is a function tampering HT
	0.22	Probability that the triggered HT in the chiplet is an information leakage HT
	0.45	Probability that the triggered HT in the chiplet is a denial-of-service HT
		Probability that the outputs of two chiplets remain consistent after being tampered with
		The average attack time of HTs is 100, 10 hr, and 6 min, simulating weak, medium, and strong attack scenarios
		The average time the HTs was active is 100 hr and 6 min, simulating the long and short duration of the HTs
		The average time for nonarbitration triggered dynamic switching chiplets is 100 hr, simulating the dynamicity of DHRCA
		The average time for the chiplet to perform a task is 100, 1 hr and 6 min, simulating long time, medium time, and short time task
K		Probability that TPAD runtime monitoring technology detects HTs when HTs are activated

Note: The parameter settings are based on the HT benchmarks and their distribution provided by the Trust-Hub [36] website. We have analyzed the chip-level HT benchmarks from Trust-Hub (100 in total) and categorized them based on their impact. Out of these benchmarks, there are 33 Trojans that tamper function, 22 HTs that leak information, and 45 HTs that cause denial-of-service.