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International Journal of Digital Multimedia Broadcasting
Volume 2008, Article ID 245305, 12 pages
Research Article

Design of a VLSI Decoder for Partially Structured LDPC Codes

1Dipartimento di Elettronica, Politecnico di Torino, 10129 Torino, Italy
2Elettronica S.p.A., 00131 Roma, Italy

Received 3 April 2008; Revised 1 July 2008; Accepted 27 August 2008

Academic Editor: Fred Daneshgaran

Copyright © 2008 Fabrizio Vacca et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.