International Journal of Digital Multimedia Broadcasting
Volume 2008 (2008), Article ID 245305, 12 pages
http://dx.doi.org/10.1155/2008/245305
Research Article
Design of a VLSI Decoder for Partially Structured LDPC Codes
1Dipartimento di Elettronica, Politecnico di Torino, 10129 Torino, Italy
2Elettronica S.p.A., 00131 Roma, Italy
Received 3 April 2008; Revised 1 July 2008; Accepted 27 August 2008
Academic Editor: Fred Daneshgaran
Copyright © 2008 Fabrizio Vacca et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Linked References
- R. Gallager, “Low-density parity-check codes,” IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21–28, 1962. View at Publisher · View at Google Scholar
- D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,” IEEE Transactions on Information Theory, vol. 45, no. 2, pp. 399–431, 1999. View at Publisher · View at Google Scholar
- A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404–412, 2002. View at Publisher · View at Google Scholar
- T. Brack, F. Kienle, and N. Wehn, “Disclosing the LDPC code decoder design space,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06), vol. 1, pp. 200–205, Munich, Germany, March 2006.
- G. Masera, F. Quaglio, and F. Vacca, “Implementation of a flexible LDPC decoder,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 6, pp. 542–546, 2007. View at Publisher · View at Google Scholar
- S.-H. Kang and I.-C. Park, “Loosely coupled memory-based edcoding architecture for low density parity check codes,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 5, pp. 1045–1056, 2006. View at Publisher · View at Google Scholar
- F. Kienle, M. J. Thul, and N. Wehn, “Implementation issues of scalable LDPC-decoders,” in Proceedings of the 3rd International Symposium on Turbo-Codes & Related Topics, pp. 291–294, Brest, France, September 2003.
- A. Tarable, S. Benedetto, and G. Montorsi, “Mapping interleaving laws to parallel turbo and LDPC decoder architectures,” IEEE Transactions on Information Theory, vol. 50, no. 9, pp. 2002–2009, 2004. View at Publisher · View at Google Scholar
- F. Quaglio, F. Vacca, C. Castellano, A. Tarable, and G. Masera, “Interconnection framework for high-throughput, flexible LDPC decoders,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '06), vol. 2, pp. 124–129, Munich, Germany, March 2006.
- E. Kim and G. S. Choi, “Diagonal low-density parity-check code for simplified routing in decoder,” in Proceedings of IEEE Workshop on Signal Processing Systems Design and Implementation (SiPS '05), vol. 2005, pp. 756–761, Athens, Greece, November 2005. View at Publisher · View at Google Scholar
- L. Dinoi, R. Martini, G. Masera, F. Quaglio, and F. Vacca, “ASIP design for partially structured LDPC codes,” Electronics Letters, vol. 42, no. 18, pp. 1048–1049, 2006. View at Publisher · View at Google Scholar
- T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 619–637, 2001. View at Publisher · View at Google Scholar
- L. Ping, W. K. Leung, and N. Phamdo, “Low density parity check codes with semi-random parity check matrix,” Electronics Letters, vol. 35, no. 1, pp. 38–39, 1999. View at Publisher · View at Google Scholar
- M. Yang, W. E. Ryan, and Y. Li, “Design of efficiently encodable moderate-length high-rate irregular LDPC codes,” IEEE Transactions on Communications, vol. 52, no. 4, pp. 564–571, 2004. View at Publisher · View at Google Scholar
- Y. Zhang, W. E. Ryan, and Y. Li, “Structured eIRA codes with low floors,” in Proceedings of IEEE International Symposium on Information Theory (ISIT '05), vol. 2005, pp. 174–178, Adelaide, Australia, September 2005. View at Publisher · View at Google Scholar
- S.-Y. Chung, T. J. Richardson, and R. L. Urbanke, “Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 657–670, 2001. View at Publisher · View at Google Scholar
- G. Durisi, L. Dinoi, and S. Benedetto, “eIRA codes for coded modulation systems,” in Proceedings of IEEE International Conference on Communications (ICC '06), vol. 3, pp. 1125–1130, Istanbul, Turkey, June 2006. View at Publisher · View at Google Scholar
- X.-Y. Hu, E. Eleftheriou, and D.-M. Arnold, “Progressive edge-growth tanner graphs,” in Proceedings of IEEE Global Communications Conference (GLOBECOM '01), vol. 2, pp. 995–1001, San Antonio, Tex, USA, November 2001.
- T. Tian, C. Jones, J. D. Villasenor, and R. D. Wesel, “Construction of irregular LDPC codes with low error floors,” in Proceedings of IEEE International Conference on Communications (ICC '03), vol. 5, pp. 3125–3129, Anchorage, Alaska, USA, May 2003. View at Publisher · View at Google Scholar
- A. Ramamoorthy and R. Wesel, “Construction of short block length irregular low-density parity-check codes,” in Proceedings of IEEE International Conference on Communications (ICC '04), vol. 1, pp. 410–414, Paris, France, June 2004. View at Publisher · View at Google Scholar
- L. Dinoi, F. Sottile, and S. Benedetto, “Design of variable-rate irregular LDPC codes with low error floor,” in Proceedings of IEEE International Conference on Communications (ICC '05), vol. 1, pp. 647–651, Seoul, Korea, May 2005. View at Publisher · View at Google Scholar
- G. Richter and A. Hof, “On a construction method of irregular LDPC codes without small stopping sets,” in Proceedings of IEEE International Conference on Communications (ICC '06), vol. 3, pp. 1119–1124, Istanbul, Turkey, June 2006. View at Publisher · View at Google Scholar
- L. Dinoi, F. Sottile, and S. Benedetto, “Design of versatile eIRA codes for parallel decoders,” to appear in IEEE Transactions on Communications.
- http://glaros.dtc.umn.edu/gkhome/views/metis.
- D. J. C. MacKay, “Encyclopedia of sparse graph codes,” http://www.inference.phy.cam.ac.uk/mackay/codes/data.html.
- T. Brack, M. Alles, T. Lehnigk-Emden et al., “Low complexity LDPC code decoders for next generation standards,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07), pp. 331–336, Nice, France, April 2007. View at Publisher · View at Google Scholar
- X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, “An 8.29 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 m CMOS process,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 672–683, 2008. View at Publisher · View at Google Scholar
- C.-H. Liu, S.-W. Yen, C.-L. Chen et al., “An LDPC decoder chip based on self-routing network for IEEE 802.16e applications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 684–694, 2008. View at Publisher · View at Google Scholar
- D. Oh and K. K. Parhi, “Performance of quantized min-sum decoding algorithms for irregular LDPC codes,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '07), pp. 2758–2761, New Orleans, La, USA, May 2007. View at Publisher · View at Google Scholar
- J. Zhang and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE Transactions on Communications, vol. 53, no. 2, pp. 209–213, 2005. View at Publisher · View at Google Scholar